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rockchip: rk3399: Save and restore RX_CAL_DQS values 

We were getting far off values on resume for the RX_CAL_DQS values.
This saves and restores the values for suspend/resume until the root
of the problem is figured out

Signed-off-by: Derek Basehore <dbasehore@chromium.org>
This commit is contained in:
Derek Basehore 2017-01-31 00:20:19 -08:00 committed by Xing Zheng
parent 4dbab5d27f
commit 951752dd6c
2 changed files with 21 additions and 1 deletions
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1
plat/rockchip/rk3399/drivers/dram/dram.h
View File

@ -159,6 +159,7 @@ struct rk3399_sdram_params {
struct rk3399_ddr_pctl_regs pctl_regs;
struct rk3399_ddr_pi_regs pi_regs;
struct rk3399_ddr_publ_regs phy_regs;
uint32_t rx_cal_dqs[2][4];
};
extern __sramdata struct rk3399_sdram_params sdram_config;

21
plat/rockchip/rk3399/drivers/dram/suspend.c
View File

@ -611,6 +611,7 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
struct rk3399_sdram_params *sdram_params)
{
uint32_t count;
uint32_t byte;
mmio_setbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
mmio_setbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
@ -642,6 +643,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
}
mmio_clrbits_32(CTL_REG(0, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(0, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[0][byte]);
}
if (channel_mask & (1 << 1)) {
count = 0;
@ -655,6 +662,12 @@ static __sramfunc int pctl_start(uint32_t channel_mask,
}
mmio_clrbits_32(CTL_REG(1, 68), PWRUP_SREFRESH_EXIT);
/* Restore the PHY_RX_CAL_DQS value */
for (byte = 0; byte < 4; byte++)
mmio_clrsetbits_32(PHY_REG(1, 57 + 128 * byte),
0xfff << 16,
sdram_params->rx_cal_dqs[1][byte]);
}
return 0;
@ -667,7 +680,7 @@ void dmc_save(void)
uint32_t *params_pi;
uint32_t *params_phy;
uint32_t refdiv, postdiv2, postdiv1, fbdiv;
uint32_t tmp;
uint32_t tmp, ch, byte;
params_ctl = sdram_params->pctl_regs.denali_ctl;
params_pi = sdram_params->pi_regs.denali_pi;
@ -707,6 +720,12 @@ void dmc_save(void)
sram_regcpy((uintptr_t)&params_phy[768], PHY_REG(0, 768), 38);
sram_regcpy((uintptr_t)&params_phy[896], PHY_REG(0, 896), 63);
for (ch = 0; ch < sdram_params->num_channels; ch++) {
for (byte = 0; byte < 4; byte++)
sdram_params->rx_cal_dqs[ch][byte] = (0xfff << 16) &
mmio_read_32(PHY_REG(ch, 57 + byte * 128));
}
/* set DENALI_PHY_957_DATA.PHY_DLL_RST_EN = 0x1 */
params_phy[957] &= ~(0x3 << 24);
params_phy[957] |= 1 << 24;