meson/gxl: Initial port of Amlogic Meson S905x (GXL)
The Amlogic Meson S905x is a SoC with a quad core Arm Cortex-A53 running at 1.5Ghz. It also contains a Cortex-M3 used as SCP. This port is a minimal implementation of BL31 capable of booting mainline U-Boot and Linux: - Partial SCPI support. - Basic PSCI support (CPU_ON, SYSTEM_RESET, SYSTEM_OFF). - GICv2 driver set up. - Basic SIP services (read efuse data, enable/disable JTAG). This port has been tested on a lepotato. Signed-off-by: Antonio Nino Diaz <antonio.ninodiaz@arm.com> Signed-off-by: Remi Pommarel <repk@triplefau.lt>
This commit is contained in:
Antonio Nino Diaz
Remi Pommarel
parent
0a4bf763f3
commit
95d0d13ce2
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <assert_macros.S>
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#include <platform_def.h>
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.globl plat_crash_console_flush
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.globl plat_crash_console_init
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.globl plat_crash_console_putc
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.globl platform_mem_init
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.globl plat_is_my_cpu_primary
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.globl plat_my_core_pos
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.globl plat_reset_handler
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.globl plat_gxbb_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_my_core_pos(void);
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* -----------------------------------------------------
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*/
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func plat_my_core_pos
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mrs x0, mpidr_el1
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b plat_gxbb_calc_core_pos
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endfunc plat_my_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
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* -----------------------------------------------------
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*/
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func plat_gxbb_calc_core_pos
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and x0, x0, #MPIDR_CPU_MASK
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ret
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endfunc plat_gxbb_calc_core_pos
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/* -----------------------------------------------------
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* unsigned int plat_is_my_cpu_primary(void);
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* -----------------------------------------------------
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*/
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func plat_is_my_cpu_primary
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mrs x0, mpidr_el1
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and x0, x0, #(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK)
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cmp x0, #GXBB_PRIMARY_CPU
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cset w0, eq
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ret
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endfunc plat_is_my_cpu_primary
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/* ---------------------------------------------
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* void platform_mem_init(void);
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* ---------------------------------------------
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*/
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func platform_mem_init
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ret
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endfunc platform_mem_init
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/* ---------------------------------------------
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* int plat_crash_console_init(void)
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* ---------------------------------------------
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*/
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func plat_crash_console_init
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mov_imm x0, GXBB_UART0_AO_BASE
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mov_imm x1, GXBB_UART0_AO_CLK_IN_HZ
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mov_imm x2, GXBB_UART_BAUDRATE
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b console_meson_init
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endfunc plat_crash_console_init
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/* ---------------------------------------------
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* int plat_crash_console_putc(int c)
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* Clobber list : x1, x2
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* ---------------------------------------------
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*/
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func plat_crash_console_putc
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mov_imm x1, GXBB_UART0_AO_BASE
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b console_meson_core_putc
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endfunc plat_crash_console_putc
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/* ---------------------------------------------
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* int plat_crash_console_flush()
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* Out : return -1 on error else return 0.
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* Clobber list : x0, x1
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* ---------------------------------------------
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*/
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func plat_crash_console_flush
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mov_imm x0, GXBB_UART0_AO_BASE
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b console_meson_core_flush
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endfunc plat_crash_console_flush
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/* ---------------------------------------------
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* void plat_reset_handler(void);
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* ---------------------------------------------
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*/
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func plat_reset_handler
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ret
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endfunc plat_reset_handler
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <drivers/arm/gicv2.h>
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#include <common/interrupt_props.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include "gxl_private.h"
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/*
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* Placeholder variables for copying the arguments that have been passed to
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* BL31 from BL2.
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*/
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static entry_point_info_t bl33_image_ep_info;
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/*******************************************************************************
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* Return a pointer to the 'entry_point_info' structure of the next image for
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* the security state specified. BL33 corresponds to the non-secure image type
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* while BL32 corresponds to the secure image type. A NULL pointer is returned
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* if the image does not exist.
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******************************************************************************/
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entry_point_info_t *bl31_plat_get_next_image_ep_info(uint32_t type)
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{
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entry_point_info_t *next_image_info;
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assert(type == NON_SECURE);
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next_image_info = &bl33_image_ep_info;
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/* None of the images can have 0x0 as the entrypoint. */
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if (next_image_info->pc != 0U) {
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return next_image_info;
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} else {
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return NULL;
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}
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}
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/*******************************************************************************
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* Perform any BL31 early platform setup. Here is an opportunity to copy
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* parameters passed by the calling EL (S-EL1 in BL2 & S-EL3 in BL1) before
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* they are lost (potentially). This needs to be done before the MMU is
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* initialized so that the memory layout can be used while creating page
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* tables. BL2 has flushed this information to memory, so we are guaranteed
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* to pick up good data.
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******************************************************************************/
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struct gxbb_bl31_param {
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param_header_t h;
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image_info_t *bl31_image_info;
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entry_point_info_t *bl32_ep_info;
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image_info_t *bl32_image_info;
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entry_point_info_t *bl33_ep_info;
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image_info_t *bl33_image_info;
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};
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void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
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u_register_t arg2, u_register_t arg3)
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{
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struct gxbb_bl31_param *from_bl2;
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/* Initialize the console to provide early debug support */
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gxbb_console_init();
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/*
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* In debug builds, we pass a special value in 'arg1' to verify platform
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* parameters from BL2 to BL31. In release builds it's not used.
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*/
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assert(arg1 == GXBB_BL31_PLAT_PARAM_VAL);
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/* Check that params passed from BL2 are not NULL. */
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from_bl2 = (struct gxbb_bl31_param *) arg0;
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/* Check params passed from BL2 are not NULL. */
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assert(from_bl2 != NULL);
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assert(from_bl2->h.type == PARAM_BL31);
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assert(from_bl2->h.version >= VERSION_1);
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/*
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* Copy BL33 entry point information. It is stored in Secure RAM, in
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* BL2's address space.
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*/
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bl33_image_ep_info = *from_bl2->bl33_ep_info;
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if (bl33_image_ep_info.pc == 0U) {
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ERROR("BL31: BL33 entrypoint not obtained from BL2\n");
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panic();
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}
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}
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void bl31_plat_arch_setup(void)
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{
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gxbb_setup_page_tables();
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enable_mmu_el3(0);
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}
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/*******************************************************************************
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* GICv2 driver setup information
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******************************************************************************/
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static const interrupt_prop_t gxbb_interrupt_props[] = {
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INTR_PROP_DESC(IRQ_SEC_PHY_TIMER, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_0, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_1, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_2, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_3, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_4, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_5, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_6, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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INTR_PROP_DESC(IRQ_SEC_SGI_7, GIC_HIGHEST_SEC_PRIORITY,
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GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),
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};
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static const gicv2_driver_data_t gxbb_gic_data = {
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.gicd_base = GXBB_GICD_BASE,
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.gicc_base = GXBB_GICC_BASE,
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.interrupt_props = gxbb_interrupt_props,
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.interrupt_props_num = ARRAY_SIZE(gxbb_interrupt_props),
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};
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void bl31_platform_setup(void)
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{
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mhu_secure_init();
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gicv2_driver_init(&gxbb_gic_data);
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gicv2_distif_init();
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gicv2_pcpu_distif_init();
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gicv2_cpuif_enable();
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// gxbb_thermal_unknown();
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}
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <assert.h>
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#include <common/bl_common.h>
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#include <common/debug.h>
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#include <common/ep_info.h>
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#include <bl31/interrupt_mgmt.h>
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#include <meson_console.h>
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#include <lib/mmio.h>
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#include <platform_def.h>
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#include <stdint.h>
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#include <lib/xlat_tables/xlat_tables_v2.h>
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/*******************************************************************************
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* Platform memory map regions
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******************************************************************************/
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#define MAP_NSDRAM0 MAP_REGION_FLAT(GXBB_NSDRAM0_BASE, \
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GXBB_NSDRAM0_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_NSDRAM1 MAP_REGION_FLAT(GXBB_NSDRAM1_BASE, \
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GXBB_NSDRAM1_SIZE, \
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MT_MEMORY | MT_RW | MT_NS)
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#define MAP_SEC_DEVICE0 MAP_REGION_FLAT(GXBB_SEC_DEVICE0_BASE, \
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GXBB_SEC_DEVICE0_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE1 MAP_REGION_FLAT(GXBB_SEC_DEVICE1_BASE, \
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GXBB_SEC_DEVICE1_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_TZRAM MAP_REGION_FLAT(GXBB_TZRAM_BASE, \
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GXBB_TZRAM_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE2 MAP_REGION_FLAT(GXBB_SEC_DEVICE2_BASE, \
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GXBB_SEC_DEVICE2_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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#define MAP_SEC_DEVICE3 MAP_REGION_FLAT(GXBB_SEC_DEVICE3_BASE, \
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GXBB_SEC_DEVICE3_SIZE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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static const mmap_region_t gxbb_mmap[] = {
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MAP_NSDRAM0,
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MAP_NSDRAM1,
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MAP_SEC_DEVICE0,
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MAP_SEC_DEVICE1,
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MAP_TZRAM,
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MAP_SEC_DEVICE2,
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MAP_SEC_DEVICE3,
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{0}
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};
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/*******************************************************************************
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* Per-image regions
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******************************************************************************/
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#define MAP_BL31 MAP_REGION_FLAT(BL31_BASE, \
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BL31_END - BL31_BASE, \
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MT_MEMORY | MT_RW | MT_SECURE)
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#define MAP_BL_CODE MAP_REGION_FLAT(BL_CODE_BASE, \
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BL_CODE_END - BL_CODE_BASE, \
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MT_CODE | MT_SECURE)
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#define MAP_BL_RO_DATA MAP_REGION_FLAT(BL_RO_DATA_BASE, \
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BL_RO_DATA_END - BL_RO_DATA_BASE, \
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MT_RO_DATA | MT_SECURE)
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#define MAP_BL_COHERENT MAP_REGION_FLAT(BL_COHERENT_RAM_BASE, \
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BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, \
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MT_DEVICE | MT_RW | MT_SECURE)
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/*******************************************************************************
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* Function that sets up the translation tables.
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******************************************************************************/
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void gxbb_setup_page_tables(void)
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{
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#if IMAGE_BL31
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const mmap_region_t gxbb_bl_mmap[] = {
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MAP_BL31,
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MAP_BL_CODE,
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MAP_BL_RO_DATA,
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#if USE_COHERENT_MEM
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MAP_BL_COHERENT,
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#endif
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{0}
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};
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#endif
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mmap_add(gxbb_bl_mmap);
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mmap_add(gxbb_mmap);
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init_xlat_tables();
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}
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/*******************************************************************************
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* Function that sets up the console
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******************************************************************************/
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static console_meson_t gxbb_console;
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void gxbb_console_init(void)
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{
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int rc = console_meson_register(GXBB_UART0_AO_BASE,
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GXBB_UART0_AO_CLK_IN_HZ,
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GXBB_UART_BAUDRATE,
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&gxbb_console);
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if (rc == 0) {
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/*
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* The crash console doesn't use the multi console API, it uses
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* the core console functions directly. It is safe to call panic
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* and let it print debug information.
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*/
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panic();
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}
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console_set_scope(&gxbb_console.console,
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CONSOLE_FLAG_BOOT | CONSOLE_FLAG_RUNTIME);
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}
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/*******************************************************************************
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* Function that returns the system counter frequency
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******************************************************************************/
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unsigned int plat_get_syscnt_freq2(void)
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{
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uint32_t val;
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val = mmio_read_32(GXBB_SYS_CPU_CFG7);
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val &= 0xFDFFFFFF;
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mmio_write_32(GXBB_SYS_CPU_CFG7, val);
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val = mmio_read_32(GXBB_AO_TIMESTAMP_CNTL);
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val &= 0xFFFFFE00;
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mmio_write_32(GXBB_AO_TIMESTAMP_CNTL, val);
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return GXBB_OSC24M_CLK_IN_HZ;
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}
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef GXBB_DEF_H
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#define GXBB_DEF_H
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#include <lib/utils_def.h>
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/*******************************************************************************
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* System oscillator
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******************************************************************************/
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#define GXBB_OSC24M_CLK_IN_HZ ULL(24000000) /* 24 MHz */
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/*******************************************************************************
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* Memory regions
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******************************************************************************/
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#define GXBB_NSDRAM0_BASE UL(0x01000000)
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#define GXBB_NSDRAM0_SIZE UL(0x0F000000)
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#define GXBB_NSDRAM1_BASE UL(0x10000000)
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#define GXBB_NSDRAM1_SIZE UL(0x00100000)
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#define BL31_BASE UL(0x05100000)
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#define BL31_SIZE UL(0x000C0000)
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#define BL31_LIMIT (BL31_BASE + BL31_SIZE)
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/* Shared memory used for SMC services */
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#define GXBB_SHARE_MEM_INPUT_BASE UL(0x050FE000)
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#define GXBB_SHARE_MEM_OUTPUT_BASE UL(0x050FF000)
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#define GXBB_SEC_DEVICE0_BASE UL(0xC0000000)
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#define GXBB_SEC_DEVICE0_SIZE UL(0x09000000)
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#define GXBB_SEC_DEVICE1_BASE UL(0xD0040000)
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#define GXBB_SEC_DEVICE1_SIZE UL(0x00008000)
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#define GXBB_TZRAM_BASE UL(0xD9000000)
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#define GXBB_TZRAM_SIZE UL(0x00014000)
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/* Top 0xC000 bytes (up to 0xD9020000) used by BL2 */
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/* Mailboxes */
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#define GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD UL(0xD9013800)
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#define GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD UL(0xD9013A00)
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#define GXBB_PSCI_MAILBOX_BASE UL(0xD9013F00)
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// * [ 1K] 0xD901_3800 - 0xD901_3BFF Secure Mailbox (3)
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// * [ 1K] 0xD901_3400 - 0xD901_37FF High Mailbox (2) *
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// * [ 1K] 0xD901_3000 - 0xD901_33FF High Mailbox (1) *
|
||||
|
||||
#define GXBB_TZROM_BASE UL(0xD9040000)
|
||||
#define GXBB_TZROM_SIZE UL(0x00010000)
|
||||
|
||||
#define GXBB_SEC_DEVICE2_BASE UL(0xDA000000)
|
||||
#define GXBB_SEC_DEVICE2_SIZE UL(0x00200000)
|
||||
|
||||
#define GXBB_SEC_DEVICE3_BASE UL(0xDA800000)
|
||||
#define GXBB_SEC_DEVICE3_SIZE UL(0x00200000)
|
||||
|
||||
/*******************************************************************************
|
||||
* GIC-400 and interrupt handling related constants
|
||||
******************************************************************************/
|
||||
#define GXBB_GICD_BASE UL(0xC4301000)
|
||||
#define GXBB_GICC_BASE UL(0xC4302000)
|
||||
|
||||
#define IRQ_SEC_PHY_TIMER 29
|
||||
|
||||
#define IRQ_SEC_SGI_0 8
|
||||
#define IRQ_SEC_SGI_1 9
|
||||
#define IRQ_SEC_SGI_2 10
|
||||
#define IRQ_SEC_SGI_3 11
|
||||
#define IRQ_SEC_SGI_4 12
|
||||
#define IRQ_SEC_SGI_5 13
|
||||
#define IRQ_SEC_SGI_6 14
|
||||
#define IRQ_SEC_SGI_7 15
|
||||
|
||||
/*******************************************************************************
|
||||
* UART definitions
|
||||
******************************************************************************/
|
||||
#define GXBB_UART0_AO_BASE UL(0xC81004C0)
|
||||
#define GXBB_UART0_AO_CLK_IN_HZ GXBB_OSC24M_CLK_IN_HZ
|
||||
#define GXBB_UART_BAUDRATE U(115200)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory-mapped I/O Registers
|
||||
******************************************************************************/
|
||||
#define GXBB_AO_TIMESTAMP_CNTL UL(0xC81000B4)
|
||||
|
||||
#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
|
||||
|
||||
#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
|
||||
|
||||
#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
|
||||
#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
|
||||
#define GXBB_HIU_MAILBOX_CLR_0 UL(0xDA83C40C)
|
||||
#define GXBB_HIU_MAILBOX_SET_3 UL(0xDA83C428)
|
||||
#define GXBB_HIU_MAILBOX_STAT_3 UL(0xDA83C42C)
|
||||
#define GXBB_HIU_MAILBOX_CLR_3 UL(0xDA83C430)
|
||||
|
||||
/*******************************************************************************
|
||||
* System Monitor Call IDs and arguments
|
||||
******************************************************************************/
|
||||
#define GXBB_SM_GET_SHARE_MEM_INPUT_BASE U(0x82000020)
|
||||
#define GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE U(0x82000021)
|
||||
|
||||
#define GXBB_SM_EFUSE_READ U(0x82000030)
|
||||
#define GXBB_SM_EFUSE_USER_MAX U(0x82000033)
|
||||
|
||||
#define GXBB_SM_JTAG_ON U(0x82000040)
|
||||
#define GXBB_SM_JTAG_OFF U(0x82000041)
|
||||
|
||||
#define GXBB_JTAG_STATE_ON U(0)
|
||||
#define GXBB_JTAG_STATE_OFF U(1)
|
||||
|
||||
#define GXBB_JTAG_M3_AO U(0)
|
||||
#define GXBB_JTAG_M3_EE U(1)
|
||||
#define GXBB_JTAG_A53_AO U(2)
|
||||
#define GXBB_JTAG_A53_EE U(3)
|
||||
|
||||
#endif /* GXBB_DEF_H */
|
||||
|
|
@ -0,0 +1,25 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
#define EFUSE_BASE 0x140
|
||||
#define EFUSE_SIZE 0xC0
|
||||
|
||||
uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size)
|
||||
{
|
||||
if ((uint64_t)(offset + size) > (uint64_t)EFUSE_SIZE)
|
||||
return 0;
|
||||
|
||||
return scpi_efuse_read(dst, offset + EFUSE_BASE, size);
|
||||
}
|
||||
|
||||
uint64_t gxbb_efuse_user_max(void)
|
||||
{
|
||||
return EFUSE_SIZE;
|
||||
}
|
||||
|
|
@ -0,0 +1,52 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <lib/bakery_lock.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
static DEFINE_BAKERY_LOCK(mhu_lock);
|
||||
|
||||
void mhu_secure_message_start(void)
|
||||
{
|
||||
bakery_lock_get(&mhu_lock);
|
||||
|
||||
while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
|
||||
;
|
||||
}
|
||||
|
||||
void mhu_secure_message_send(uint32_t msg)
|
||||
{
|
||||
mmio_write_32(GXBB_HIU_MAILBOX_SET_3, msg);
|
||||
|
||||
while (mmio_read_32(GXBB_HIU_MAILBOX_STAT_3) != 0)
|
||||
;
|
||||
}
|
||||
|
||||
uint32_t mhu_secure_message_wait(void)
|
||||
{
|
||||
uint32_t val;
|
||||
|
||||
do {
|
||||
val = mmio_read_32(GXBB_HIU_MAILBOX_STAT_0);
|
||||
} while (val == 0);
|
||||
|
||||
return val;
|
||||
}
|
||||
|
||||
void mhu_secure_message_end(void)
|
||||
{
|
||||
mmio_write_32(GXBB_HIU_MAILBOX_CLR_0, 0xFFFFFFFF);
|
||||
|
||||
bakery_lock_release(&mhu_lock);
|
||||
}
|
||||
|
||||
void mhu_secure_init(void)
|
||||
{
|
||||
bakery_lock_init(&mhu_lock);
|
||||
|
||||
mmio_write_32(GXBB_HIU_MAILBOX_CLR_3, 0xFFFFFFFF);
|
||||
}
|
||||
|
|
@ -0,0 +1,193 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch_helpers.h>
|
||||
#include <assert.h>
|
||||
#include <drivers/console.h>
|
||||
#include <common/debug.h>
|
||||
#include <errno.h>
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <lib/psci/psci.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
#define SCPI_POWER_ON 0
|
||||
#define SCPI_POWER_RETENTION 1
|
||||
#define SCPI_POWER_OFF 3
|
||||
|
||||
#define SCPI_SYSTEM_SHUTDOWN 0
|
||||
#define SCPI_SYSTEM_REBOOT 1
|
||||
|
||||
static uintptr_t gxbb_sec_entrypoint;
|
||||
static volatile uint32_t gxbb_cpu0_go;
|
||||
|
||||
static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
|
||||
{
|
||||
unsigned int core = plat_gxbb_calc_core_pos(mpidr);
|
||||
uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
|
||||
|
||||
mmio_write_64(cpu_mailbox_addr, value);
|
||||
flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t));
|
||||
}
|
||||
|
||||
static void __dead2 gxbb_system_reset(void)
|
||||
{
|
||||
INFO("BL31: PSCI_SYSTEM_RESET\n");
|
||||
|
||||
uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
|
||||
|
||||
NOTICE("BL31: Reboot reason: 0x%x\n", status);
|
||||
|
||||
status &= 0xFFFF0FF0;
|
||||
|
||||
console_flush();
|
||||
|
||||
mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
|
||||
|
||||
int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
wfi();
|
||||
|
||||
ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static void __dead2 gxbb_system_off(void)
|
||||
{
|
||||
INFO("BL31: PSCI_SYSTEM_OFF\n");
|
||||
|
||||
unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
|
||||
|
||||
if (ret != 0) {
|
||||
ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret);
|
||||
panic();
|
||||
}
|
||||
|
||||
gxbb_program_mailbox(read_mpidr_el1(), 0);
|
||||
|
||||
wfi();
|
||||
|
||||
ERROR("BL31: PSCI_SYSTEM_OFF: Operation not handled\n");
|
||||
panic();
|
||||
}
|
||||
|
||||
static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
|
||||
{
|
||||
unsigned int core = plat_gxbb_calc_core_pos(mpidr);
|
||||
|
||||
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
|
||||
if (core == GXBB_PRIMARY_CPU) {
|
||||
VERBOSE("BL31: Releasing CPU0 from wait loop...\n");
|
||||
|
||||
gxbb_cpu0_go = 1;
|
||||
flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
|
||||
sizeof(gxbb_cpu0_go));
|
||||
dsb();
|
||||
isb();
|
||||
|
||||
sev();
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint);
|
||||
scpi_set_css_power_state(mpidr,
|
||||
SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
|
||||
dmbsy();
|
||||
sev();
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
||||
static void gxbb_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
||||
{
|
||||
unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
|
||||
|
||||
assert(target_state->pwr_domain_state[MPIDR_AFFLVL0] ==
|
||||
PLAT_LOCAL_STATE_OFF);
|
||||
|
||||
if (core == GXBB_PRIMARY_CPU) {
|
||||
gxbb_cpu0_go = 0;
|
||||
flush_dcache_range((uintptr_t)&gxbb_cpu0_go,
|
||||
sizeof(gxbb_cpu0_go));
|
||||
dsb();
|
||||
isb();
|
||||
}
|
||||
|
||||
gicv2_pcpu_distif_init();
|
||||
gicv2_cpuif_enable();
|
||||
}
|
||||
|
||||
static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
|
||||
{
|
||||
u_register_t mpidr = read_mpidr_el1();
|
||||
unsigned int core = plat_gxbb_calc_core_pos(mpidr);
|
||||
uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
|
||||
|
||||
mmio_write_32(addr, 0xFFFFFFFF);
|
||||
flush_dcache_range(addr, sizeof(uint32_t));
|
||||
|
||||
gicv2_cpuif_disable();
|
||||
|
||||
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
|
||||
if (core == GXBB_PRIMARY_CPU)
|
||||
return;
|
||||
|
||||
scpi_set_css_power_state(mpidr,
|
||||
SCPI_POWER_OFF, SCPI_POWER_ON, SCPI_POWER_ON);
|
||||
}
|
||||
|
||||
static void __dead2 gxbb_pwr_domain_pwr_down_wfi(const psci_power_state_t
|
||||
*target_state)
|
||||
{
|
||||
unsigned int core = plat_gxbb_calc_core_pos(read_mpidr_el1());
|
||||
|
||||
/* CPU0 can't be turned OFF, emulate it with a WFE loop */
|
||||
if (core == GXBB_PRIMARY_CPU) {
|
||||
VERBOSE("BL31: CPU0 entering wait loop...\n");
|
||||
|
||||
while (gxbb_cpu0_go == 0)
|
||||
wfe();
|
||||
|
||||
VERBOSE("BL31: CPU0 resumed.\n");
|
||||
|
||||
write_rmr_el3(RMR_EL3_RR_BIT | RMR_EL3_AA64_BIT);
|
||||
}
|
||||
|
||||
dsbsy();
|
||||
|
||||
for (;;)
|
||||
wfi();
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Platform handlers and setup function.
|
||||
******************************************************************************/
|
||||
static const plat_psci_ops_t gxbb_ops = {
|
||||
.pwr_domain_on = gxbb_pwr_domain_on,
|
||||
.pwr_domain_on_finish = gxbb_pwr_domain_on_finish,
|
||||
.pwr_domain_off = gxbb_pwr_domain_off,
|
||||
.pwr_domain_pwr_down_wfi = gxbb_pwr_domain_pwr_down_wfi,
|
||||
.system_off = gxbb_system_off,
|
||||
.system_reset = gxbb_system_reset,
|
||||
};
|
||||
|
||||
int plat_setup_psci_ops(uintptr_t sec_entrypoint,
|
||||
const plat_psci_ops_t **psci_ops)
|
||||
{
|
||||
gxbb_sec_entrypoint = sec_entrypoint;
|
||||
*psci_ops = &gxbb_ops;
|
||||
gxbb_cpu0_go = 0;
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -0,0 +1,38 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef GXBB_PRIVATE_H
|
||||
#define GXBB_PRIVATE_H
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
/* Utility functions */
|
||||
unsigned int plat_gxbb_calc_core_pos(u_register_t mpidr);
|
||||
void gxbb_console_init(void);
|
||||
void gxbb_setup_page_tables(void);
|
||||
|
||||
/* MHU functions */
|
||||
void mhu_secure_message_start(void);
|
||||
void mhu_secure_message_send(uint32_t msg);
|
||||
uint32_t mhu_secure_message_wait(void);
|
||||
void mhu_secure_message_end(void);
|
||||
void mhu_secure_init(void);
|
||||
|
||||
/* SCPI functions */
|
||||
void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
|
||||
uint32_t cluster_state, uint32_t css_state);
|
||||
uint32_t scpi_sys_power_state(uint64_t system_state);
|
||||
void scpi_jtag_set_state(uint32_t state, uint8_t select);
|
||||
uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size);
|
||||
void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
|
||||
uint32_t arg2, uint32_t arg3);
|
||||
|
||||
/* Peripherals */
|
||||
void gxbb_thermal_unknown(void);
|
||||
uint64_t gxbb_efuse_read(void *dst, uint32_t offset, uint32_t size);
|
||||
uint64_t gxbb_efuse_user_max(void);
|
||||
|
||||
#endif /* GXBB_PRIVATE_H */
|
||||
|
|
@ -0,0 +1,137 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <platform_def.h>
|
||||
#include <string.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
#define SIZE_SHIFT 20
|
||||
#define SIZE_MASK 0x1FF
|
||||
|
||||
/*
|
||||
* Note: The Amlogic SCP firmware uses the legacy SCPI protocol.
|
||||
*/
|
||||
#define SCPI_CMD_SET_CSS_POWER_STATE 0x04
|
||||
#define SCPI_CMD_SET_SYS_POWER_STATE 0x08
|
||||
|
||||
#define SCPI_CMD_JTAG_SET_STATE 0xC0
|
||||
#define SCPI_CMD_EFUSE_READ 0xC2
|
||||
|
||||
static inline uint32_t scpi_cmd(uint32_t command, uint32_t size)
|
||||
{
|
||||
return command | (size << SIZE_SHIFT);
|
||||
}
|
||||
|
||||
void scpi_secure_message_send(uint32_t command, uint32_t size)
|
||||
{
|
||||
mhu_secure_message_send(scpi_cmd(command, size));
|
||||
}
|
||||
|
||||
uint32_t scpi_secure_message_receive(void **message_out, size_t *size_out)
|
||||
{
|
||||
uint32_t response = mhu_secure_message_wait();
|
||||
|
||||
size_t size = (response >> SIZE_SHIFT) & SIZE_MASK;
|
||||
|
||||
response &= ~(SIZE_MASK << SIZE_SHIFT);
|
||||
|
||||
if (size_out != NULL)
|
||||
*size_out = size;
|
||||
|
||||
if (message_out != NULL)
|
||||
*message_out = (void *)GXBB_MHU_SECURE_SCP_TO_AP_PAYLOAD;
|
||||
|
||||
return response;
|
||||
}
|
||||
|
||||
void scpi_set_css_power_state(u_register_t mpidr, uint32_t cpu_state,
|
||||
uint32_t cluster_state, uint32_t css_state)
|
||||
{
|
||||
uint32_t state = (mpidr & 0x0F) | /* CPU ID */
|
||||
((mpidr & 0xF00) >> 4) | /* Cluster ID */
|
||||
(cpu_state << 8) |
|
||||
(cluster_state << 12) |
|
||||
(css_state << 16);
|
||||
|
||||
mhu_secure_message_start();
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, state);
|
||||
mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_CSS_POWER_STATE, 4));
|
||||
mhu_secure_message_wait();
|
||||
mhu_secure_message_end();
|
||||
}
|
||||
|
||||
uint32_t scpi_sys_power_state(uint64_t system_state)
|
||||
{
|
||||
uint32_t *response;
|
||||
size_t size;
|
||||
|
||||
mhu_secure_message_start();
|
||||
mmio_write_8(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, system_state);
|
||||
mhu_secure_message_send(scpi_cmd(SCPI_CMD_SET_SYS_POWER_STATE, 1));
|
||||
scpi_secure_message_receive((void *)&response, &size);
|
||||
mhu_secure_message_end();
|
||||
|
||||
return *response;
|
||||
}
|
||||
|
||||
void scpi_jtag_set_state(uint32_t state, uint8_t select)
|
||||
{
|
||||
assert(state <= GXBB_JTAG_STATE_OFF);
|
||||
|
||||
if (select > GXBB_JTAG_A53_EE) {
|
||||
WARN("BL31: Invalid JTAG select (0x%x).\n", select);
|
||||
return;
|
||||
}
|
||||
|
||||
mhu_secure_message_start();
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD,
|
||||
(state << 8) | (uint32_t)select);
|
||||
mhu_secure_message_send(scpi_cmd(SCPI_CMD_JTAG_SET_STATE, 4));
|
||||
mhu_secure_message_wait();
|
||||
mhu_secure_message_end();
|
||||
}
|
||||
|
||||
uint32_t scpi_efuse_read(void *dst, uint32_t base, uint32_t size)
|
||||
{
|
||||
uint32_t *response;
|
||||
size_t resp_size;
|
||||
|
||||
if (size > 0x1FC)
|
||||
return 0;
|
||||
|
||||
mhu_secure_message_start();
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD, base);
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 4, size);
|
||||
mhu_secure_message_send(scpi_cmd(SCPI_CMD_EFUSE_READ, 8));
|
||||
scpi_secure_message_receive((void *)&response, &resp_size);
|
||||
mhu_secure_message_end();
|
||||
|
||||
/*
|
||||
* response[0] is the size of the response message.
|
||||
* response[1 ... N] are the contents.
|
||||
*/
|
||||
if (*response != 0)
|
||||
memcpy(dst, response + 1, *response);
|
||||
|
||||
return *response;
|
||||
}
|
||||
|
||||
void scpi_unknown_thermal(uint32_t arg0, uint32_t arg1,
|
||||
uint32_t arg2, uint32_t arg3)
|
||||
{
|
||||
mhu_secure_message_start();
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x0, arg0);
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x4, arg1);
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0x8, arg2);
|
||||
mmio_write_32(GXBB_MHU_SECURE_AP_TO_SCP_PAYLOAD + 0xC, arg3);
|
||||
mhu_secure_message_send(scpi_cmd(0xC3, 16));
|
||||
mhu_secure_message_wait();
|
||||
mhu_secure_message_end();
|
||||
}
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <common/debug.h>
|
||||
#include <lib/mmio.h>
|
||||
#include <platform_def.h>
|
||||
#include <common/runtime_svc.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* This function is responsible for handling all SiP calls
|
||||
******************************************************************************/
|
||||
static uintptr_t gxbb_sip_handler(uint32_t smc_fid,
|
||||
u_register_t x1, u_register_t x2,
|
||||
u_register_t x3, u_register_t x4,
|
||||
void *cookie, void *handle,
|
||||
u_register_t flags)
|
||||
{
|
||||
switch (smc_fid) {
|
||||
|
||||
case GXBB_SM_GET_SHARE_MEM_INPUT_BASE:
|
||||
SMC_RET1(handle, GXBB_SHARE_MEM_INPUT_BASE);
|
||||
|
||||
case GXBB_SM_GET_SHARE_MEM_OUTPUT_BASE:
|
||||
SMC_RET1(handle, GXBB_SHARE_MEM_OUTPUT_BASE);
|
||||
|
||||
case GXBB_SM_EFUSE_READ:
|
||||
{
|
||||
void *dst = (void *)GXBB_SHARE_MEM_OUTPUT_BASE;
|
||||
uint64_t ret = gxbb_efuse_read(dst, (uint32_t)x1, x2);
|
||||
|
||||
SMC_RET1(handle, ret);
|
||||
}
|
||||
case GXBB_SM_EFUSE_USER_MAX:
|
||||
SMC_RET1(handle, gxbb_efuse_user_max());
|
||||
|
||||
case GXBB_SM_JTAG_ON:
|
||||
scpi_jtag_set_state(GXBB_JTAG_STATE_ON, x1);
|
||||
SMC_RET1(handle, 0);
|
||||
|
||||
case GXBB_SM_JTAG_OFF:
|
||||
scpi_jtag_set_state(GXBB_JTAG_STATE_OFF, x1);
|
||||
SMC_RET1(handle, 0);
|
||||
|
||||
default:
|
||||
ERROR("BL31: Unhandled SIP SMC: 0x%08x\n", smc_fid);
|
||||
break;
|
||||
}
|
||||
|
||||
SMC_RET1(handle, SMC_UNK);
|
||||
}
|
||||
|
||||
DECLARE_RT_SVC(
|
||||
gxbb_sip_handler,
|
||||
|
||||
OEN_SIP_START,
|
||||
OEN_SIP_END,
|
||||
SMC_TYPE_FAST,
|
||||
NULL,
|
||||
gxbb_sip_handler
|
||||
);
|
||||
|
|
@ -0,0 +1,27 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
static int32_t modules_initialized = -1;
|
||||
|
||||
/*******************************************************************************
|
||||
* Unknown commands related to something thermal-related
|
||||
******************************************************************************/
|
||||
void gxbb_thermal_unknown(void)
|
||||
{
|
||||
uint16_t ret;
|
||||
|
||||
if (modules_initialized == -1) {
|
||||
scpi_efuse_read(&ret, 0, 2);
|
||||
modules_initialized = ret;
|
||||
}
|
||||
|
||||
scpi_unknown_thermal(10, 2, /* thermal */
|
||||
13, 1); /* thermalver */
|
||||
}
|
||||
|
|
@ -0,0 +1,53 @@
|
|||
/*
|
||||
* Copyright (c) 2015-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <arch.h>
|
||||
#include <platform_def.h>
|
||||
#include <stdint.h>
|
||||
|
||||
#include "gxl_private.h"
|
||||
|
||||
/* The power domain tree descriptor */
|
||||
static unsigned char power_domain_tree_desc[] = {
|
||||
/* Number of root nodes */
|
||||
PLATFORM_CLUSTER_COUNT,
|
||||
/* Number of children for the first node */
|
||||
PLATFORM_CLUSTER0_CORE_COUNT
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* This function returns the ARM default topology tree information.
|
||||
******************************************************************************/
|
||||
const unsigned char *plat_get_power_domain_tree_desc(void)
|
||||
{
|
||||
return power_domain_tree_desc;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This function implements a part of the critical interface between the psci
|
||||
* generic layer and the platform that allows the former to query the platform
|
||||
* to convert an MPIDR to a unique linear index. An error code (-1) is returned
|
||||
* in case the MPIDR is invalid.
|
||||
******************************************************************************/
|
||||
int plat_core_pos_by_mpidr(u_register_t mpidr)
|
||||
{
|
||||
unsigned int cluster_id, cpu_id;
|
||||
|
||||
mpidr &= MPIDR_AFFINITY_MASK;
|
||||
if (mpidr & ~(MPIDR_CLUSTER_MASK | MPIDR_CPU_MASK))
|
||||
return -1;
|
||||
|
||||
cluster_id = (mpidr >> MPIDR_AFF1_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
cpu_id = (mpidr >> MPIDR_AFF0_SHIFT) & MPIDR_AFFLVL_MASK;
|
||||
|
||||
if (cluster_id >= PLATFORM_CLUSTER_COUNT)
|
||||
return -1;
|
||||
|
||||
if (cpu_id >= PLATFORM_MAX_CPUS_PER_CLUSTER)
|
||||
return -1;
|
||||
|
||||
return plat_gxbb_calc_core_pos(mpidr);
|
||||
}
|
||||
|
|
@ -0,0 +1,71 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLAT_MACROS_S
|
||||
#define PLAT_MACROS_S
|
||||
|
||||
#include <drivers/arm/gicv2.h>
|
||||
#include <platform_def.h>
|
||||
|
||||
.section .rodata.gic_reg_name, "aS"
|
||||
|
||||
gicc_regs:
|
||||
.asciz "gicc_hppir", "gicc_ahppir", "gicc_ctlr", ""
|
||||
gicd_pend_reg:
|
||||
.asciz "gicd_ispendr regs (Offsets 0x200 - 0x278)\n Offset:\t\t\tvalue\n"
|
||||
newline:
|
||||
.asciz "\n"
|
||||
spacer:
|
||||
.asciz ":\t\t0x"
|
||||
|
||||
/* ---------------------------------------------
|
||||
* The below required platform porting macro
|
||||
* prints out relevant GIC and CCI registers
|
||||
* whenever an unhandled exception is taken in
|
||||
* BL31.
|
||||
* Clobbers: x0 - x10, x16, x17, sp
|
||||
* ---------------------------------------------
|
||||
*/
|
||||
.macro plat_crash_print_regs
|
||||
|
||||
/* GICC registers */
|
||||
|
||||
mov_imm x17, GXBB_GICC_BASE
|
||||
|
||||
adr x6, gicc_regs
|
||||
ldr w8, [x17, #GICC_HPPIR]
|
||||
ldr w9, [x17, #GICC_AHPPIR]
|
||||
ldr w10, [x17, #GICC_CTLR]
|
||||
bl str_in_crash_buf_print
|
||||
|
||||
/* GICD registers */
|
||||
|
||||
mov_imm x16, GXBB_GICD_BASE
|
||||
|
||||
add x7, x16, #GICD_ISPENDR
|
||||
adr x4, gicd_pend_reg
|
||||
bl asm_print_str
|
||||
|
||||
gicd_ispendr_loop:
|
||||
sub x4, x7, x16
|
||||
cmp x4, #0x280
|
||||
b.eq exit_print_gic_regs
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, spacer
|
||||
bl asm_print_str
|
||||
|
||||
ldr x4, [x7], #8
|
||||
bl asm_print_hex
|
||||
|
||||
adr x4, newline
|
||||
bl asm_print_str
|
||||
b gicd_ispendr_loop
|
||||
exit_print_gic_regs:
|
||||
|
||||
.endm
|
||||
|
||||
#endif /* PLAT_MACROS_S */
|
||||
|
|
@ -0,0 +1,66 @@
|
|||
/*
|
||||
* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef PLATFORM_DEF_H
|
||||
#define PLATFORM_DEF_H
|
||||
|
||||
#include <arch.h>
|
||||
#include <lib/utils_def.h>
|
||||
|
||||
#include "../gxl_def.h"
|
||||
|
||||
#define PLATFORM_LINKER_FORMAT "elf64-littleaarch64"
|
||||
#define PLATFORM_LINKER_ARCH aarch64
|
||||
|
||||
/* Special value used to verify platform parameters from BL2 to BL31 */
|
||||
#define GXBB_BL31_PLAT_PARAM_VAL ULL(0x0F1E2D3C4B5A6978)
|
||||
|
||||
#define PLATFORM_STACK_SIZE UL(0x1000)
|
||||
|
||||
#define PLATFORM_MAX_CPUS_PER_CLUSTER U(4)
|
||||
#define PLATFORM_CLUSTER_COUNT U(1)
|
||||
#define PLATFORM_CLUSTER0_CORE_COUNT PLATFORM_MAX_CPUS_PER_CLUSTER
|
||||
#define PLATFORM_CORE_COUNT PLATFORM_CLUSTER0_CORE_COUNT
|
||||
|
||||
#define GXBB_PRIMARY_CPU U(0)
|
||||
|
||||
#define PLAT_MAX_PWR_LVL MPIDR_AFFLVL1
|
||||
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CLUSTER_COUNT + \
|
||||
PLATFORM_CORE_COUNT)
|
||||
|
||||
#define PLAT_MAX_RET_STATE U(1)
|
||||
#define PLAT_MAX_OFF_STATE U(2)
|
||||
|
||||
/* Local power state for power domains in Run state. */
|
||||
#define PLAT_LOCAL_STATE_RUN U(0)
|
||||
/* Local power state for retention. Valid only for CPU power domains */
|
||||
#define PLAT_LOCAL_STATE_RET U(1)
|
||||
/* Local power state for power-down. Valid for CPU and cluster power domains. */
|
||||
#define PLAT_LOCAL_STATE_OFF U(2)
|
||||
|
||||
/*
|
||||
* Macros used to parse state information from State-ID if it is using the
|
||||
* recommended encoding for State-ID.
|
||||
*/
|
||||
#define PLAT_LOCAL_PSTATE_WIDTH U(4)
|
||||
#define PLAT_LOCAL_PSTATE_MASK ((U(1) << PLAT_LOCAL_PSTATE_WIDTH) - 1)
|
||||
|
||||
/*
|
||||
* Some data must be aligned on the biggest cache line size in the platform.
|
||||
* This is known only to the platform as it might have a combination of
|
||||
* integrated and external caches.
|
||||
*/
|
||||
#define CACHE_WRITEBACK_SHIFT U(6)
|
||||
#define CACHE_WRITEBACK_GRANULE (U(1) << CACHE_WRITEBACK_SHIFT)
|
||||
|
||||
/* Memory-related defines */
|
||||
#define PLAT_PHY_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
#define PLAT_VIRT_ADDR_SPACE_SIZE (ULL(1) << 32)
|
||||
|
||||
#define MAX_MMAP_REGIONS 12
|
||||
#define MAX_XLAT_TABLES 6
|
||||
|
||||
#endif /* PLATFORM_DEF_H */
|
||||
|
|
@ -0,0 +1,76 @@
|
|||
#
|
||||
# Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
|
||||
#
|
||||
# SPDX-License-Identifier: BSD-3-Clause
|
||||
#
|
||||
|
||||
include lib/xlat_tables_v2/xlat_tables.mk
|
||||
|
||||
PLAT_INCLUDES := -Iinclude/drivers/meson/ \
|
||||
-Iplat/meson/gxl/include
|
||||
|
||||
GXBB_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
|
||||
drivers/arm/gic/v2/gicv2_main.c \
|
||||
drivers/arm/gic/v2/gicv2_helpers.c \
|
||||
plat/common/plat_gicv2.c
|
||||
|
||||
PLAT_BL_COMMON_SOURCES := drivers/meson/console/aarch64/meson_console.S \
|
||||
plat/meson/gxl/gxl_common.c \
|
||||
plat/meson/gxl/gxl_topology.c \
|
||||
${XLAT_TABLES_LIB_SRCS}
|
||||
|
||||
BL31_SOURCES += lib/cpus/aarch64/cortex_a53.S \
|
||||
plat/common/plat_psci_common.c \
|
||||
plat/meson/gxl/aarch64/gxl_helpers.S \
|
||||
plat/meson/gxl/gxl_bl31_setup.c \
|
||||
plat/meson/gxl/gxl_efuse.c \
|
||||
plat/meson/gxl/gxl_mhu.c \
|
||||
plat/meson/gxl/gxl_pm.c \
|
||||
plat/meson/gxl/gxl_scpi.c \
|
||||
plat/meson/gxl/gxl_sip_svc.c \
|
||||
plat/meson/gxl/gxl_thermal.c \
|
||||
${GXBB_GIC_SOURCES}
|
||||
|
||||
# Tune compiler for Cortex-A53
|
||||
ifeq ($(notdir $(CC)),armclang)
|
||||
TF_CFLAGS_aarch64 += -mcpu=cortex-a53
|
||||
else ifneq ($(findstring clang,$(notdir $(CC))),)
|
||||
TF_CFLAGS_aarch64 += -mcpu=cortex-a53
|
||||
else
|
||||
TF_CFLAGS_aarch64 += -mtune=cortex-a53
|
||||
endif
|
||||
|
||||
# Build config flags
|
||||
# ------------------
|
||||
|
||||
# Enable all errata workarounds for Cortex-A53
|
||||
ERRATA_A53_855873 := 1
|
||||
ERRATA_A53_819472 := 1
|
||||
ERRATA_A53_824069 := 1
|
||||
ERRATA_A53_827319 := 1
|
||||
|
||||
WORKAROUND_CVE_2017_5715 := 0
|
||||
|
||||
# Have different sections for code and rodata
|
||||
SEPARATE_CODE_AND_RODATA := 1
|
||||
|
||||
# Use Coherent memory
|
||||
USE_COHERENT_MEM := 1
|
||||
|
||||
# Use multi console API
|
||||
MULTI_CONSOLE_API := 1
|
||||
|
||||
# Verify build config
|
||||
# -------------------
|
||||
|
||||
ifneq (${MULTI_CONSOLE_API}, 1)
|
||||
$(error Error: gxl needs MULTI_CONSOLE_API=1)
|
||||
endif
|
||||
|
||||
ifneq (${RESET_TO_BL31}, 0)
|
||||
$(error Error: gxl needs RESET_TO_BL31=0)
|
||||
endif
|
||||
|
||||
ifeq (${ARCH},aarch32)
|
||||
$(error Error: AArch32 not supported on gxl)
|
||||
endif
|
||||
Loading…
Reference in New Issue