zynqmp: pm: Correct WDT clock database
WDT used by APU is FPD_WDT. FPD WDT clock is controlled by FPD_SLCR.WDT_CLK_SEL register. Correct the same in WDT clock database. As per FPD_SLCR.WDT_CLK_SEL register, there can be only two parents of WDT clock not three. Fix the same by correcting it's parents in clock database. Signed-off-by: Tejas Patel <tejas.patel@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Acked-by: Jolly Shah <jolly.shah@xilinx.com>
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@ -2022,12 +2022,11 @@ static struct pm_clock clocks[] = {
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},
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[CLK_WDT] = {
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.name = "wdt",
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.control_reg = IOU_SLCR_WDT_CLK_SEL,
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.control_reg = FPD_SLCR_WDT_CLK_SEL,
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.status_reg = 0,
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.parents = &((int32_t []) {
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CLK_TOPSW_LSBUS,
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EXT_CLK_SWDT0 | CLK_EXTERNAL_PARENT,
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EXT_CLK_SWDT1 | CLK_EXTERNAL_PARENT,
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CLK_NA_PARENT
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}),
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.nodes = &wdt_nodes,
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@ -201,6 +201,7 @@
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#define ACTLR_EL3_L2ACTLR_BIT (1 << 6)
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#define ACTLR_EL3_CPUACTLR_BIT (1 << 0)
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#define FPD_SLCR_BASEADDR U(0xFD610000)
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#define IOU_SLCR_BASEADDR U(0xFF180000)
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#define ZYNQMP_RPU_GLBL_CNTL U(0xFF9A0000)
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@ -325,7 +326,7 @@
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#define CRL_APB_TIMESTAMP_REF_CTRL (CRL_APB_CLK_BASE + 0x108)
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#define IOU_SLCR_GEM_CLK_CTRL (IOU_SLCR_BASEADDR + 0x308)
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#define IOU_SLCR_CAN_MIO_CTRL (IOU_SLCR_BASEADDR + 0x304)
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#define IOU_SLCR_WDT_CLK_SEL (IOU_SLCR_BASEADDR + 0x300)
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#define FPD_SLCR_WDT_CLK_SEL (FPD_SLCR_BASEADDR + 0x100)
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/* Global general storage register base address */
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#define GGS_BASEADDR (0xFFD80030U)
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