Add basic NOR flash driver for ARM platforms
FVP and Juno platforms include a NOR flash memory to store and load the FIP, the kernel or a ramdisk. This NOR flash is arranged as 2 x 16 bit flash devices and can be programmed using CFI standard commands. This patch provides a basic API to write single 32 bit words of data into the NOR flash. Functions to lock/unlock blocks against erase or write operations are also provided. Change-Id: I1da7ad3105b1ea409c976adc863954787cbd90d2
This commit is contained in:
Juan Castillo
parent
dc2d4038b9
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9784dbda11
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __NORFLASH_H_
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#define __NORFLASH_H_
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#include <stdint.h>
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/* First bus cycle */
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#define NOR_CMD_READ_ARRAY 0xFF
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#define NOR_CMD_READ_ID_CODE 0x90
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#define NOR_CMD_READ_QUERY 0x98
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#define NOR_CMD_READ_STATUS_REG 0x70
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#define NOR_CMD_CLEAR_STATUS_REG 0x50
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#define NOR_CMD_WRITE_TO_BUFFER 0xE8
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#define NOR_CMD_WORD_PROGRAM 0x40
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#define NOR_CMD_BLOCK_ERASE 0x20
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#define NOR_CMD_LOCK_UNLOCK 0x60
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/* Second bus cycle */
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#define NOR_LOCK_BLOCK 0x01
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#define NOR_UNLOCK_BLOCK 0xD0
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/* Status register bits */
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#define NOR_DWS (1 << 7)
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#define NOR_ESS (1 << 6)
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#define NOR_ES (1 << 5)
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#define NOR_PS (1 << 4)
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#define NOR_VPPS (1 << 3)
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#define NOR_PSS (1 << 2)
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#define NOR_BLS (1 << 1)
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#define NOR_BWS (1 << 0)
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/* Public API */
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void nor_send_cmd(uintptr_t base_addr, unsigned long cmd);
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int nor_word_program(uintptr_t base_addr, unsigned long data);
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void nor_lock(uintptr_t base_addr);
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void nor_unlock(uintptr_t base_addr);
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#endif /* __NORFLASH_H_ */
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@ -0,0 +1,124 @@
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/*
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* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#include <errno.h>
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#include <mmio.h>
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#include <norflash.h>
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/* Helper macros to access two flash banks in parallel */
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#define NOR_2X16(d) ((d << 16) | (d & 0xffff))
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/*
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* DWS ready poll retries. The number of retries in this driver have been
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* obtained empirically from Juno. FVP implements a zero wait state NOR flash
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* model
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*/
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#define DWS_WORD_PROGRAM_RETRIES 1000
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/*
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* Poll Write State Machine. Return values:
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* 0 = WSM ready
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* -EBUSY = WSM busy after the number of retries
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*/
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static int nor_poll_dws(uintptr_t base_addr, unsigned int retries)
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{
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uint32_t status;
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int ret;
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for (;;) {
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nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
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status = mmio_read_32(base_addr);
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if ((status & NOR_DWS) &&
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(status & (NOR_DWS << 16))) {
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ret = 0;
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break;
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}
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if (retries-- == 0) {
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ret = -EBUSY;
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break;
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}
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}
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return ret;
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}
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void nor_send_cmd(uintptr_t base_addr, unsigned long cmd)
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{
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mmio_write_32(base_addr, NOR_2X16(cmd));
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}
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/*
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* Return values:
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* 0 = success
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* -EBUSY = WSM not ready
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* -EPERM = Device protected or Block locked
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*/
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int nor_word_program(uintptr_t base_addr, unsigned long data)
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{
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uint32_t status;
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int ret;
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/* Set the device in write word mode */
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nor_send_cmd(base_addr, NOR_CMD_WORD_PROGRAM);
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mmio_write_32(base_addr, data);
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ret = nor_poll_dws(base_addr, DWS_WORD_PROGRAM_RETRIES);
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if (ret != 0) {
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goto word_program_end;
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}
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/* Full status check */
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nor_send_cmd(base_addr, NOR_CMD_READ_STATUS_REG);
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status = mmio_read_32(base_addr);
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if (status & (NOR_PS | NOR_BLS)) {
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nor_send_cmd(base_addr, NOR_CMD_CLEAR_STATUS_REG);
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ret = -EPERM;
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}
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word_program_end:
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nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
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return ret;
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}
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void nor_lock(uintptr_t base_addr)
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{
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nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
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mmio_write_32(base_addr, NOR_2X16(NOR_LOCK_BLOCK));
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nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
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}
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void nor_unlock(uintptr_t base_addr)
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{
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nor_send_cmd(base_addr, NOR_CMD_LOCK_UNLOCK);
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mmio_write_32(base_addr, NOR_2X16(NOR_UNLOCK_BLOCK));
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nor_send_cmd(base_addr, NOR_CMD_READ_ARRAY);
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}
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