Merge changes from topic "st_mapping_update" into integration
* changes: feat(stm32mp1): enable BL2_IN_XIP_MEM to remove relocation sections refactor(stm32mp1): reduce MMU memory regions and split XLAT by context feat(st): map 2MB for ROM code fix(stm32mp1): restrict DEVICE2 mapping in BL2
This commit is contained in:
Madhukar Pappireddy
TrustedFirmware Code Review
commit
97c9114787
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@ -1,13 +1,11 @@
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/*
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* Copyright (c) 2019, STMicroelectronics - All Rights Reserved
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* Copyright (c) 2019-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <errno.h>
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#include <platform_def.h>
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#include <common/debug.h>
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#include <drivers/io/io_storage.h>
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#include <drivers/st/bsec.h>
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@ -15,6 +13,8 @@
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#include <lib/xlat_tables/xlat_tables_v2.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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static const struct stm32mp_auth_ops *auth_ops;
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void stm32mp_init_auth(struct stm32mp_auth_ops *init_ptr)
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@ -47,7 +47,7 @@ int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer)
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}
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ret = mmap_add_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_BASE,
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STM32MP_ROM_SIZE, MT_CODE | MT_SECURE);
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STM32MP_ROM_SIZE_2MB_ALIGNED, MT_CODE | MT_SECURE);
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if (ret != 0) {
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return ret;
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}
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@ -85,6 +85,6 @@ int stm32mp_auth_image(boot_api_image_header_t *header, uintptr_t buffer)
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}
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err:
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mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE);
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mmap_remove_dynamic_region(STM32MP_ROM_BASE, STM32MP_ROM_SIZE_2MB_ALIGNED);
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return ret;
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}
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -68,6 +68,13 @@
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#define BL2_LIMIT (STM32MP_BL2_BASE + \
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STM32MP_BL2_SIZE)
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#define BL2_RO_BASE STM32MP_BL2_RO_BASE
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#define BL2_RO_LIMIT (STM32MP_BL2_RO_BASE + \
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STM32MP_BL2_RO_SIZE)
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#define BL2_RW_BASE STM32MP_BL2_RW_BASE
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#define BL2_RW_LIMIT (STM32MP_BL2_RW_BASE + \
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STM32MP_BL2_RW_SIZE)
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/*******************************************************************************
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* BL32 specific defines.
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******************************************************************************/
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@ -16,6 +16,7 @@ STM32MP_USE_STM32IMAGE ?= 0
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ifneq ($(STM32MP_USE_STM32IMAGE),1)
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ENABLE_PIE := 1
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BL2_IN_XIP_MEM := 1
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endif
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STM32_TF_VERSION ?= 0
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -57,7 +57,11 @@ SECTIONS
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* The strongest and only alignment contraint is MMU 4K page.
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* Indeed as images below will be removed, 4K pages will be re-used.
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*/
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#if SEPARATE_CODE_AND_RODATA
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. = ( STM32MP_BL2_RO_BASE - STM32MP_BINARY_BASE );
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#else
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. = ( STM32MP_BL2_BASE - STM32MP_BINARY_BASE );
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#endif
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__BL2_IMAGE_START__ = .;
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*(.bl2_image*)
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__BL2_IMAGE_END__ = .;
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@ -68,6 +68,7 @@
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******************************************************************************/
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#define STM32MP_ROM_BASE U(0x00000000)
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#define STM32MP_ROM_SIZE U(0x00020000)
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#define STM32MP_ROM_SIZE_2MB_ALIGNED U(0x00200000)
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#define STM32MP_SYSRAM_BASE U(0x2FFC0000)
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#define STM32MP_SYSRAM_SIZE U(0x00040000)
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@ -110,15 +111,25 @@ enum ddr_type {
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(STM32MP_PARAM_LOAD_SIZE + \
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STM32MP_HEADER_SIZE))
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/* BL2 and BL32/sp_min require 4 tables */
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#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
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/* BL2 and BL32/sp_min require finer granularity tables */
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#if defined(IMAGE_BL2)
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#define MAX_XLAT_TABLES U(2) /* 8 KB for mapping */
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#endif
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#if defined(IMAGE_BL32)
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#define MAX_XLAT_TABLES U(4) /* 16 KB for mapping */
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#endif
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/*
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* MAX_MMAP_REGIONS is usually:
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* BL stm32mp1_mmap size + mmap regions in *_plat_arch_setup
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*/
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#if defined(IMAGE_BL2)
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#define MAX_MMAP_REGIONS 11
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#if STM32MP_USB_PROGRAMMER
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#define MAX_MMAP_REGIONS 8
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#else
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#define MAX_MMAP_REGIONS 7
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#endif
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#endif
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#define STM32MP_BL33_BASE (STM32MP_DDR_BASE + U(0x100000))
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@ -1,5 +1,5 @@
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/*
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* Copyright (C) 2021, STMicroelectronics - All Rights Reserved
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* Copyright (C) 2021-2022, STMicroelectronics - All Rights Reserved
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -10,9 +10,10 @@
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#define STM32MP_DDR_S_SIZE U(0x01E00000) /* 30 MB */
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#define STM32MP_DDR_SHMEM_SIZE U(0x00200000) /* 2 MB */
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#define STM32MP_BL2_SIZE U(0x0001B000) /* 108 KB for BL2 */
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#define STM32MP_BL2_DTB_SIZE U(0x00006000) /* 24 KB for DTB */
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#define STM32MP_BL32_SIZE U(0x00019000) /* 100 KB for BL32 */
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#define STM32MP_BL2_RO_SIZE U(0x00011000) /* 68 KB */
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#define STM32MP_BL2_SIZE U(0x00016000) /* 88 KB for BL2 */
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#define STM32MP_BL2_DTB_SIZE U(0x00007000) /* 28 KB for DTB */
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#define STM32MP_BL32_SIZE U(0x0001B000) /* 108 KB for BL32 */
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#define STM32MP_BL32_DTB_SIZE U(0x00005000) /* 20 KB for DTB */
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#define STM32MP_FW_CONFIG_MAX_SIZE PAGE_SIZE /* 4 KB for FCONF DTB */
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#define STM32MP_HW_CONFIG_MAX_SIZE U(0x40000) /* 256 KB for HW config DTB */
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@ -21,6 +22,15 @@
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_SIZE)
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#define STM32MP_BL2_RO_BASE STM32MP_BL2_BASE
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#define STM32MP_BL2_RW_BASE (STM32MP_BL2_RO_BASE + \
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STM32MP_BL2_RO_SIZE)
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#define STM32MP_BL2_RW_SIZE (STM32MP_SEC_SYSRAM_BASE + \
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STM32MP_SEC_SYSRAM_SIZE - \
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STM32MP_BL2_RW_BASE)
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#define STM32MP_BL2_DTB_BASE (STM32MP_BL2_BASE - \
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STM32MP_BL2_DTB_SIZE)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2015-2021, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2015-2022, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -82,7 +82,9 @@
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static const mmap_region_t stm32mp1_mmap[] = {
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MAP_SEC_SYSRAM,
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MAP_DEVICE1,
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#if STM32MP_RAW_NAND
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MAP_DEVICE2,
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#endif
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{0}
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};
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#endif
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