andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

Add workaround for errata 790748 for Cortex-A75 

Internal timing conditions might cause the CPU to stop processing
interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this.

Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba
Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
This commit is contained in:
Louis Mayencourt 2019-02-25 14:57:57 +00:00
parent 5f5d1ed7d5
commit 98551591f5
3 changed files with 47 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
docs/cpu-specific-build-macros.rst
View File

@ -142,6 +142,9 @@ For Cortex-A75, the following errata build flags are defined :
- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
CPU. This needs to be enabled only for revision r0p0 of the CPU.
- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
CPU. This needs to be enabled only for revision r0p0 of the CPU.
DSU Errata Workarounds
----------------------

36
lib/cpus/aarch64/cortex_a75.S
View File

@ -38,6 +38,34 @@ func check_errata_764081
b cpu_rev_var_ls
endfunc check_errata_764081
/* --------------------------------------------------
* Errata Workaround for Cortex A75 Errata #790748.
* This applies only to revision r0p0 of Cortex A75.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a75_790748_wa
/*
* Compare x0 against revision r0p0
*/
mov x17, x30
bl check_errata_790748
cbz x0, 1f
mrs x1, CORTEX_A75_CPUACTLR_EL1
orr x1, x1 ,#(1 << 13)
msr CORTEX_A75_CPUACTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a75_790748_wa
func check_errata_790748
mov x1, #0x00
b cpu_rev_var_ls
endfunc check_errata_790748
/* -------------------------------------------------
* The CPU Ops reset function for Cortex-A75.
* -------------------------------------------------
@ -45,11 +73,18 @@ endfunc check_errata_764081
func cortex_a75_reset_func
mov x19, x30
bl cpu_get_rev_var
mov x18, x0
#if ERRATA_A75_764081
mov x0, x18
bl errata_a75_764081_wa
#endif
#if ERRATA_A75_790748
mov x0, x18
bl errata_a75_790748_wa
#endif
#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
cpu_check_csv2 x0, 1f
adr x0, wa_cve_2017_5715_bpiall_vbar
@ -148,6 +183,7 @@ func cortex_a75_errata_report
* checking functions of each errata.
*/
report_errata ERRATA_A75_764081, cortex_a75, 764081
report_errata ERRATA_A75_790748, cortex_a75, 790748
report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184

8
lib/cpus/cpu-ops.mk
View File

@ -127,6 +127,10 @@ ERRATA_A73_855423 ?=0
# only to revision <= r0p0 of the Cortex A75 cpu.
ERRATA_A75_764081 ?=0
# Flag to apply erratum 790748 workaround during reset. This erratum applies
# only to revision <= r0p0 of the Cortex A75 cpu.
ERRATA_A75_790748 ?=0
# Flag to apply T32 CLREX workaround during reset. This erratum applies
# only to r0p0 and r1p0 of the Neoverse N1 cpu.
ERRATA_N1_1043202 ?=1
@ -204,6 +208,10 @@ $(eval $(call add_define,ERRATA_A73_855423))
$(eval $(call assert_boolean,ERRATA_A75_764081))
$(eval $(call add_define,ERRATA_A75_764081))
# Process ERRATA_A75_790748 flag
$(eval $(call assert_boolean,ERRATA_A75_790748))
$(eval $(call add_define,ERRATA_A75_790748))
# Process ERRATA_N1_1043202 flag
$(eval $(call assert_boolean,ERRATA_N1_1043202))
$(eval $(call add_define,ERRATA_N1_1043202))