Add workaround for errata 790748 for Cortex-A75
Internal timing conditions might cause the CPU to stop processing interrupts. Set bit 13 of CPUACTLR_EL1 to prevent this. Change-Id: Ifdd19dbcdb71bb0d9609cab1315c478aaedb03ba Signed-off-by: Louis Mayencourt <louis.mayencourt@arm.com>
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@ -142,6 +142,9 @@ For Cortex-A75, the following errata build flags are defined :
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- ``ERRATA_A75_764081``: This applies errata 764081 workaround to Cortex-A75
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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- ``ERRATA_A75_790748``: This applies errata 790748 workaround to Cortex-A75
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CPU. This needs to be enabled only for revision r0p0 of the CPU.
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DSU Errata Workarounds
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----------------------
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@ -38,6 +38,34 @@ func check_errata_764081
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b cpu_rev_var_ls
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endfunc check_errata_764081
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/* --------------------------------------------------
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* Errata Workaround for Cortex A75 Errata #790748.
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* This applies only to revision r0p0 of Cortex A75.
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* Inputs:
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* x0: variant[4:7] and revision[0:3] of current cpu.
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* Shall clobber: x0-x17
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* --------------------------------------------------
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*/
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func errata_a75_790748_wa
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/*
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* Compare x0 against revision r0p0
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*/
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mov x17, x30
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bl check_errata_790748
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cbz x0, 1f
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mrs x1, CORTEX_A75_CPUACTLR_EL1
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orr x1, x1 ,#(1 << 13)
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msr CORTEX_A75_CPUACTLR_EL1, x1
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isb
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1:
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ret x17
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endfunc errata_a75_790748_wa
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func check_errata_790748
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mov x1, #0x00
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b cpu_rev_var_ls
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endfunc check_errata_790748
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/* -------------------------------------------------
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* The CPU Ops reset function for Cortex-A75.
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* -------------------------------------------------
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@ -45,11 +73,18 @@ endfunc check_errata_764081
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func cortex_a75_reset_func
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mov x19, x30
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bl cpu_get_rev_var
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mov x18, x0
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#if ERRATA_A75_764081
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mov x0, x18
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bl errata_a75_764081_wa
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#endif
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#if ERRATA_A75_790748
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mov x0, x18
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bl errata_a75_790748_wa
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#endif
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#if IMAGE_BL31 && WORKAROUND_CVE_2017_5715
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cpu_check_csv2 x0, 1f
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adr x0, wa_cve_2017_5715_bpiall_vbar
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@ -148,6 +183,7 @@ func cortex_a75_errata_report
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* checking functions of each errata.
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*/
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report_errata ERRATA_A75_764081, cortex_a75, 764081
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report_errata ERRATA_A75_790748, cortex_a75, 790748
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report_errata WORKAROUND_CVE_2017_5715, cortex_a75, cve_2017_5715
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report_errata WORKAROUND_CVE_2018_3639, cortex_a75, cve_2018_3639
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report_errata ERRATA_DSU_936184, cortex_a75, dsu_936184
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@ -127,6 +127,10 @@ ERRATA_A73_855423 ?=0
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# only to revision <= r0p0 of the Cortex A75 cpu.
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ERRATA_A75_764081 ?=0
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# Flag to apply erratum 790748 workaround during reset. This erratum applies
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# only to revision <= r0p0 of the Cortex A75 cpu.
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ERRATA_A75_790748 ?=0
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# Flag to apply T32 CLREX workaround during reset. This erratum applies
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# only to r0p0 and r1p0 of the Neoverse N1 cpu.
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ERRATA_N1_1043202 ?=1
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@ -204,6 +208,10 @@ $(eval $(call add_define,ERRATA_A73_855423))
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$(eval $(call assert_boolean,ERRATA_A75_764081))
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$(eval $(call add_define,ERRATA_A75_764081))
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# Process ERRATA_A75_790748 flag
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$(eval $(call assert_boolean,ERRATA_A75_790748))
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$(eval $(call add_define,ERRATA_A75_790748))
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# Process ERRATA_N1_1043202 flag
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$(eval $(call assert_boolean,ERRATA_N1_1043202))
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$(eval $(call add_define,ERRATA_N1_1043202))
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