Tegra: smmu: platform handler for SMMU settings
This patch empowers the platforms to provide an array with the registers that must be saved/restored across System Suspend. Original-change-by: Pritesh Raithatha <praithatha@nvidia.com> Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
parent
a8a39a50a4
commit
986e333dc3
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@ -31,407 +31,18 @@
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#include <assert.h>
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#include <bl_common.h>
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#include <debug.h>
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#include <memctrl_v2.h>
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#include <platform_def.h>
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#include <smmu.h>
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#include <string.h>
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#include <tegra_private.h>
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typedef struct smmu_regs {
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uint32_t reg;
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uint32_t val;
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} smmu_regs_t;
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#define mc_make_sid_override_cfg(name) \
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{ \
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.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
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.val = 0x00000000, \
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}
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#define mc_make_sid_security_cfg(name) \
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{ \
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.reg = TEGRA_MC_STREAMID_BASE + \
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MC_STREAMID_OVERRIDE_TO_SECURITY_CFG( \
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MC_STREAMID_OVERRIDE_CFG_ ## name), \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_sec_cfg(name) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
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.val = 0x00000000, \
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}
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/*
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* On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
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* is 0x400. So, add it to register address
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*/
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#define smmu_make_gnsr0_nsec_cfg(name) \
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{ \
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.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_smr_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr0_s2cr_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr1_cbar_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
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.val = 0x00000000, \
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}
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#define smmu_make_gnsr1_cba2r_cfg(n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
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.val = 0x00000000, \
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}
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#define make_smmu_cb_cfg(name, n) \
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{ \
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.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
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+ SMMU_CBn_ ## name, \
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.val = 0x00000000, \
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}
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#define smmu_make_smrg_group(n) \
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smmu_make_gnsr0_smr_cfg(n), \
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smmu_make_gnsr0_s2cr_cfg(n), \
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smmu_make_gnsr1_cbar_cfg(n), \
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smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */
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#define smmu_make_cb_group(n) \
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make_smmu_cb_cfg(SCTLR, n), \
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make_smmu_cb_cfg(TCR2, n), \
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make_smmu_cb_cfg(TTBR0_LO, n), \
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make_smmu_cb_cfg(TTBR0_HI, n), \
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make_smmu_cb_cfg(TCR, n), \
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make_smmu_cb_cfg(PRRR_MAIR0, n),\
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make_smmu_cb_cfg(FSR, n), \
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make_smmu_cb_cfg(FAR_LO, n), \
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make_smmu_cb_cfg(FAR_HI, n), \
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make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */
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#define smmu_bypass_cfg \
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{ \
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.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
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.val = 0x00000000, \
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}
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#define _START_OF_TABLE_ \
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{ \
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.reg = 0xCAFE05C7, \
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.val = 0x00000000, \
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}
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#define _END_OF_TABLE_ \
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{ \
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.reg = 0xFFFFFFFF, \
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.val = 0xFFFFFFFF, \
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}
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static __attribute__((aligned(16))) smmu_regs_t smmu_ctx_regs[] = {
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_START_OF_TABLE_,
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mc_make_sid_security_cfg(SCEW),
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mc_make_sid_security_cfg(AFIR),
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mc_make_sid_security_cfg(NVDISPLAYR1),
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mc_make_sid_security_cfg(XUSB_DEVR),
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mc_make_sid_security_cfg(VICSRD1),
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mc_make_sid_security_cfg(NVENCSWR),
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mc_make_sid_security_cfg(TSECSRDB),
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mc_make_sid_security_cfg(AXISW),
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mc_make_sid_security_cfg(SDMMCWAB),
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mc_make_sid_security_cfg(AONDMAW),
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mc_make_sid_security_cfg(GPUSWR2),
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mc_make_sid_security_cfg(SATAW),
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mc_make_sid_security_cfg(UFSHCW),
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mc_make_sid_security_cfg(AFIW),
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mc_make_sid_security_cfg(SDMMCR),
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mc_make_sid_security_cfg(SCEDMAW),
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mc_make_sid_security_cfg(UFSHCR),
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mc_make_sid_security_cfg(SDMMCWAA),
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mc_make_sid_security_cfg(APEDMAW),
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mc_make_sid_security_cfg(SESWR),
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mc_make_sid_security_cfg(MPCORER),
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mc_make_sid_security_cfg(PTCR),
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mc_make_sid_security_cfg(BPMPW),
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mc_make_sid_security_cfg(ETRW),
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mc_make_sid_security_cfg(GPUSRD),
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mc_make_sid_security_cfg(VICSWR),
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mc_make_sid_security_cfg(SCEDMAR),
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mc_make_sid_security_cfg(HDAW),
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mc_make_sid_security_cfg(ISPWA),
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mc_make_sid_security_cfg(EQOSW),
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mc_make_sid_security_cfg(XUSB_HOSTW),
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mc_make_sid_security_cfg(TSECSWR),
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mc_make_sid_security_cfg(SDMMCRAA),
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mc_make_sid_security_cfg(APER),
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mc_make_sid_security_cfg(VIW),
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mc_make_sid_security_cfg(APEW),
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mc_make_sid_security_cfg(AXISR),
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mc_make_sid_security_cfg(SDMMCW),
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mc_make_sid_security_cfg(BPMPDMAW),
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mc_make_sid_security_cfg(ISPRA),
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mc_make_sid_security_cfg(NVDECSWR),
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mc_make_sid_security_cfg(XUSB_DEVW),
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mc_make_sid_security_cfg(NVDECSRD),
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mc_make_sid_security_cfg(MPCOREW),
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mc_make_sid_security_cfg(NVDISPLAYR),
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mc_make_sid_security_cfg(BPMPDMAR),
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mc_make_sid_security_cfg(NVJPGSWR),
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mc_make_sid_security_cfg(NVDECSRD1),
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mc_make_sid_security_cfg(TSECSRD),
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mc_make_sid_security_cfg(NVJPGSRD),
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mc_make_sid_security_cfg(SDMMCWA),
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mc_make_sid_security_cfg(SCER),
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mc_make_sid_security_cfg(XUSB_HOSTR),
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mc_make_sid_security_cfg(VICSRD),
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mc_make_sid_security_cfg(AONDMAR),
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mc_make_sid_security_cfg(AONW),
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mc_make_sid_security_cfg(SDMMCRA),
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mc_make_sid_security_cfg(HOST1XDMAR),
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mc_make_sid_security_cfg(EQOSR),
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mc_make_sid_security_cfg(SATAR),
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mc_make_sid_security_cfg(BPMPR),
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mc_make_sid_security_cfg(HDAR),
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mc_make_sid_security_cfg(SDMMCRAB),
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mc_make_sid_security_cfg(ETRR),
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mc_make_sid_security_cfg(AONR),
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mc_make_sid_security_cfg(APEDMAR),
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mc_make_sid_security_cfg(SESRD),
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mc_make_sid_security_cfg(NVENCSRD),
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mc_make_sid_security_cfg(GPUSWR),
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mc_make_sid_security_cfg(TSECSWRB),
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mc_make_sid_security_cfg(ISPWB),
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mc_make_sid_security_cfg(GPUSRD2),
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mc_make_sid_override_cfg(APER),
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mc_make_sid_override_cfg(VICSRD),
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mc_make_sid_override_cfg(NVENCSRD),
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mc_make_sid_override_cfg(NVJPGSWR),
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mc_make_sid_override_cfg(AONW),
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mc_make_sid_override_cfg(BPMPR),
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mc_make_sid_override_cfg(BPMPW),
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mc_make_sid_override_cfg(HDAW),
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mc_make_sid_override_cfg(NVDISPLAYR1),
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mc_make_sid_override_cfg(APEDMAR),
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mc_make_sid_override_cfg(AFIR),
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mc_make_sid_override_cfg(AXISR),
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mc_make_sid_override_cfg(VICSRD1),
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mc_make_sid_override_cfg(TSECSRD),
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mc_make_sid_override_cfg(BPMPDMAW),
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mc_make_sid_override_cfg(MPCOREW),
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mc_make_sid_override_cfg(XUSB_HOSTR),
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mc_make_sid_override_cfg(GPUSWR),
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mc_make_sid_override_cfg(XUSB_DEVR),
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mc_make_sid_override_cfg(UFSHCW),
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mc_make_sid_override_cfg(XUSB_HOSTW),
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mc_make_sid_override_cfg(SDMMCWAB),
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mc_make_sid_override_cfg(SATAW),
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mc_make_sid_override_cfg(SCEDMAR),
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mc_make_sid_override_cfg(HOST1XDMAR),
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mc_make_sid_override_cfg(SDMMCWA),
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mc_make_sid_override_cfg(APEDMAW),
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mc_make_sid_override_cfg(SESWR),
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mc_make_sid_override_cfg(AXISW),
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mc_make_sid_override_cfg(AONDMAW),
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mc_make_sid_override_cfg(TSECSWRB),
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mc_make_sid_override_cfg(MPCORER),
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mc_make_sid_override_cfg(ISPWB),
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mc_make_sid_override_cfg(AONR),
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mc_make_sid_override_cfg(BPMPDMAR),
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mc_make_sid_override_cfg(HDAR),
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mc_make_sid_override_cfg(SDMMCRA),
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mc_make_sid_override_cfg(ETRW),
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mc_make_sid_override_cfg(GPUSWR2),
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mc_make_sid_override_cfg(EQOSR),
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mc_make_sid_override_cfg(TSECSWR),
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mc_make_sid_override_cfg(ETRR),
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mc_make_sid_override_cfg(NVDECSRD),
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mc_make_sid_override_cfg(TSECSRDB),
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mc_make_sid_override_cfg(SDMMCRAA),
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mc_make_sid_override_cfg(NVDECSRD1),
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mc_make_sid_override_cfg(SDMMCR),
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mc_make_sid_override_cfg(NVJPGSRD),
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mc_make_sid_override_cfg(SCEDMAW),
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mc_make_sid_override_cfg(SDMMCWAA),
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mc_make_sid_override_cfg(APEW),
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mc_make_sid_override_cfg(AONDMAR),
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mc_make_sid_override_cfg(PTCR),
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mc_make_sid_override_cfg(SCER),
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mc_make_sid_override_cfg(ISPRA),
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mc_make_sid_override_cfg(ISPWA),
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mc_make_sid_override_cfg(VICSWR),
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mc_make_sid_override_cfg(SESRD),
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mc_make_sid_override_cfg(SDMMCW),
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mc_make_sid_override_cfg(SDMMCRAB),
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mc_make_sid_override_cfg(EQOSW),
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mc_make_sid_override_cfg(GPUSRD2),
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mc_make_sid_override_cfg(SCEW),
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mc_make_sid_override_cfg(GPUSRD),
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mc_make_sid_override_cfg(NVDECSWR),
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mc_make_sid_override_cfg(XUSB_DEVW),
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mc_make_sid_override_cfg(SATAR),
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mc_make_sid_override_cfg(NVDISPLAYR),
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mc_make_sid_override_cfg(VIW),
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mc_make_sid_override_cfg(UFSHCR),
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mc_make_sid_override_cfg(NVENCSWR),
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mc_make_sid_override_cfg(AFIW),
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smmu_make_gnsr0_nsec_cfg(CR0),
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smmu_make_gnsr0_sec_cfg(IDR0),
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smmu_make_gnsr0_sec_cfg(IDR1),
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smmu_make_gnsr0_sec_cfg(IDR2),
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smmu_make_gnsr0_nsec_cfg(GFSR),
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smmu_make_gnsr0_nsec_cfg(GFSYNR0),
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smmu_make_gnsr0_nsec_cfg(GFSYNR1),
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smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
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smmu_make_gnsr0_nsec_cfg(PIDR2),
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smmu_make_smrg_group(0),
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smmu_make_smrg_group(1),
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smmu_make_smrg_group(2),
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smmu_make_smrg_group(3),
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smmu_make_smrg_group(4),
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smmu_make_smrg_group(5),
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smmu_make_smrg_group(6),
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smmu_make_smrg_group(7),
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smmu_make_smrg_group(8),
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smmu_make_smrg_group(9),
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smmu_make_smrg_group(10),
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smmu_make_smrg_group(11),
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smmu_make_smrg_group(12),
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smmu_make_smrg_group(13),
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smmu_make_smrg_group(14),
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smmu_make_smrg_group(15),
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smmu_make_smrg_group(16),
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smmu_make_smrg_group(17),
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smmu_make_smrg_group(18),
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smmu_make_smrg_group(19),
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smmu_make_smrg_group(20),
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smmu_make_smrg_group(21),
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smmu_make_smrg_group(22),
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smmu_make_smrg_group(23),
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smmu_make_smrg_group(24),
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smmu_make_smrg_group(25),
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smmu_make_smrg_group(26),
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smmu_make_smrg_group(27),
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smmu_make_smrg_group(28),
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smmu_make_smrg_group(29),
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smmu_make_smrg_group(30),
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smmu_make_smrg_group(31),
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smmu_make_smrg_group(32),
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smmu_make_smrg_group(33),
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smmu_make_smrg_group(34),
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smmu_make_smrg_group(35),
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smmu_make_smrg_group(36),
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smmu_make_smrg_group(37),
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smmu_make_smrg_group(38),
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smmu_make_smrg_group(39),
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smmu_make_smrg_group(40),
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smmu_make_smrg_group(41),
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smmu_make_smrg_group(42),
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smmu_make_smrg_group(43),
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smmu_make_smrg_group(44),
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smmu_make_smrg_group(45),
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smmu_make_smrg_group(46),
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smmu_make_smrg_group(47),
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smmu_make_smrg_group(48),
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smmu_make_smrg_group(49),
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smmu_make_smrg_group(50),
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smmu_make_smrg_group(51),
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smmu_make_smrg_group(52),
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smmu_make_smrg_group(53),
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smmu_make_smrg_group(54),
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smmu_make_smrg_group(55),
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smmu_make_smrg_group(56),
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smmu_make_smrg_group(57),
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smmu_make_smrg_group(58),
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smmu_make_smrg_group(59),
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smmu_make_smrg_group(60),
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smmu_make_smrg_group(61),
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smmu_make_smrg_group(62),
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smmu_make_smrg_group(63),
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smmu_make_cb_group(0),
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smmu_make_cb_group(1),
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smmu_make_cb_group(2),
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smmu_make_cb_group(3),
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smmu_make_cb_group(4),
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smmu_make_cb_group(5),
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smmu_make_cb_group(6),
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smmu_make_cb_group(7),
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smmu_make_cb_group(8),
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smmu_make_cb_group(9),
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smmu_make_cb_group(10),
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smmu_make_cb_group(11),
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smmu_make_cb_group(12),
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smmu_make_cb_group(13),
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smmu_make_cb_group(14),
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smmu_make_cb_group(15),
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smmu_make_cb_group(16),
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smmu_make_cb_group(17),
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smmu_make_cb_group(18),
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smmu_make_cb_group(19),
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smmu_make_cb_group(20),
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smmu_make_cb_group(21),
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smmu_make_cb_group(22),
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smmu_make_cb_group(23),
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smmu_make_cb_group(24),
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smmu_make_cb_group(25),
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smmu_make_cb_group(26),
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smmu_make_cb_group(27),
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smmu_make_cb_group(28),
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smmu_make_cb_group(29),
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smmu_make_cb_group(30),
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smmu_make_cb_group(31),
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smmu_make_cb_group(32),
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smmu_make_cb_group(33),
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smmu_make_cb_group(34),
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smmu_make_cb_group(35),
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smmu_make_cb_group(36),
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smmu_make_cb_group(37),
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smmu_make_cb_group(38),
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smmu_make_cb_group(39),
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smmu_make_cb_group(40),
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smmu_make_cb_group(41),
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smmu_make_cb_group(42),
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smmu_make_cb_group(43),
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smmu_make_cb_group(44),
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smmu_make_cb_group(45),
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smmu_make_cb_group(46),
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smmu_make_cb_group(47),
|
||||
smmu_make_cb_group(48),
|
||||
smmu_make_cb_group(49),
|
||||
smmu_make_cb_group(50),
|
||||
smmu_make_cb_group(51),
|
||||
smmu_make_cb_group(52),
|
||||
smmu_make_cb_group(53),
|
||||
smmu_make_cb_group(54),
|
||||
smmu_make_cb_group(55),
|
||||
smmu_make_cb_group(56),
|
||||
smmu_make_cb_group(57),
|
||||
smmu_make_cb_group(58),
|
||||
smmu_make_cb_group(59),
|
||||
smmu_make_cb_group(60),
|
||||
smmu_make_cb_group(61),
|
||||
smmu_make_cb_group(62),
|
||||
smmu_make_cb_group(63),
|
||||
smmu_bypass_cfg, /* TBU settings */
|
||||
_END_OF_TABLE_,
|
||||
};
|
||||
|
||||
/*
|
||||
* Save SMMU settings before "System Suspend" to TZDRAM
|
||||
*/
|
||||
void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
|
||||
{
|
||||
uint32_t i;
|
||||
smmu_regs_t *smmu_ctx_regs;
|
||||
#if DEBUG
|
||||
plat_params_from_bl2_t *params_from_bl2 = bl31_get_plat_params();
|
||||
uint64_t tzdram_base = params_from_bl2->tzdram_base;
|
||||
|
@ -449,11 +60,12 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
|
|||
|
||||
assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
|
||||
|
||||
/* index of _END_OF_TABLE_ */
|
||||
smmu_ctx_regs[0].val = ARRAY_SIZE(smmu_ctx_regs) - 1;
|
||||
/* get SMMU context table */
|
||||
smmu_ctx_regs = plat_get_smmu_ctx();
|
||||
assert(smmu_ctx_regs);
|
||||
|
||||
/* save SMMU register values */
|
||||
for (i = 1; i < ARRAY_SIZE(smmu_ctx_regs) - 1; i++)
|
||||
for (i = 1; i < smmu_ctx_regs[0].val; i++)
|
||||
smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
|
||||
|
||||
/* Save SMMU config settings */
|
||||
|
|
|
@ -624,17 +624,109 @@
|
|||
#define PGSHIFT 16
|
||||
#define CB_SIZE 0x800000
|
||||
|
||||
static inline uint32_t tegra_smmu_read_32(uint32_t off)
|
||||
{
|
||||
return mmio_read_32(TEGRA_SMMU_BASE + off);
|
||||
}
|
||||
typedef struct smmu_regs {
|
||||
uint32_t reg;
|
||||
uint32_t val;
|
||||
} smmu_regs_t;
|
||||
|
||||
#define mc_make_sid_override_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_CFG_ ## name, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define mc_make_sid_security_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_MC_STREAMID_BASE + MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(MC_STREAMID_OVERRIDE_CFG_ ## name), \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_gnsr0_sec_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_ ## name, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
/*
|
||||
* On ARM-SMMU, conditional offset to access secure aliases of non-secure registers
|
||||
* is 0x400. So, add it to register address
|
||||
*/
|
||||
#define smmu_make_gnsr0_nsec_cfg(name) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + 0x400 + SMMU_GNSR0_ ## name, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_gnsr0_smr_cfg(n) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_SMR ## n, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_gnsr0_s2cr_cfg(n) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + SMMU_GNSR0_S2CR ## n, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_gnsr1_cbar_cfg(n) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBAR ## n, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_gnsr1_cba2r_cfg(n) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + (1 << PGSHIFT) + SMMU_GNSR1_CBA2R ## n, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define make_smmu_cb_cfg(name, n) \
|
||||
{ \
|
||||
.reg = TEGRA_SMMU_BASE + (CB_SIZE >> 1) + (n * (1 << PGSHIFT)) \
|
||||
+ SMMU_CBn_ ## name, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define smmu_make_smrg_group(n) \
|
||||
smmu_make_gnsr0_smr_cfg(n), \
|
||||
smmu_make_gnsr0_s2cr_cfg(n), \
|
||||
smmu_make_gnsr1_cbar_cfg(n), \
|
||||
smmu_make_gnsr1_cba2r_cfg(n) /* don't put "," here. */
|
||||
|
||||
#define smmu_make_cb_group(n) \
|
||||
make_smmu_cb_cfg(SCTLR, n), \
|
||||
make_smmu_cb_cfg(TCR2, n), \
|
||||
make_smmu_cb_cfg(TTBR0_LO, n), \
|
||||
make_smmu_cb_cfg(TTBR0_HI, n), \
|
||||
make_smmu_cb_cfg(TCR, n), \
|
||||
make_smmu_cb_cfg(PRRR_MAIR0, n),\
|
||||
make_smmu_cb_cfg(FSR, n), \
|
||||
make_smmu_cb_cfg(FAR_LO, n), \
|
||||
make_smmu_cb_cfg(FAR_HI, n), \
|
||||
make_smmu_cb_cfg(FSYNR0, n) /* don't put "," here. */
|
||||
|
||||
#define smmu_bypass_cfg \
|
||||
{ \
|
||||
.reg = TEGRA_MC_BASE + MC_SMMU_BYPASS_CONFIG, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define _START_OF_TABLE_ \
|
||||
{ \
|
||||
.reg = 0xCAFE05C7, \
|
||||
.val = 0x00000000, \
|
||||
}
|
||||
|
||||
#define _END_OF_TABLE_ \
|
||||
{ \
|
||||
.reg = 0xFFFFFFFF, \
|
||||
.val = 0xFFFFFFFF, \
|
||||
}
|
||||
|
||||
static inline void tegra_smmu_write_32(uint32_t off, uint32_t val)
|
||||
{
|
||||
mmio_write_32(TEGRA_SMMU_BASE + off, val);
|
||||
}
|
||||
|
||||
void tegra_smmu_init(void);
|
||||
void tegra_smmu_save_context(uint64_t smmu_ctx_addr);
|
||||
smmu_regs_t *plat_get_smmu_ctx(void);
|
||||
|
||||
#endif /*__SMMU_H */
|
||||
|
|
|
@ -0,0 +1,326 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* Permission is hereby granted, free of charge, to any person obtaining a
|
||||
* copy of this software and associated documentation files (the "Software"),
|
||||
* to deal in the Software without restriction, including without limitation
|
||||
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
||||
* and/or sell copies of the Software, and to permit persons to whom the
|
||||
* Software is furnished to do so, subject to the following conditions:
|
||||
*
|
||||
* The above copyright notice and this permission notice shall be included in
|
||||
* all copies or substantial portions of the Software.
|
||||
*
|
||||
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
||||
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
||||
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
||||
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
||||
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
||||
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
||||
* DEALINGS IN THE SOFTWARE.
|
||||
*/
|
||||
|
||||
#include <bl_common.h>
|
||||
#include <smmu.h>
|
||||
#include <tegra_def.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Array to hold SMMU context for Tegra186
|
||||
******************************************************************************/
|
||||
static __attribute__((aligned(16))) smmu_regs_t tegra186_smmu_context[] = {
|
||||
_START_OF_TABLE_,
|
||||
mc_make_sid_security_cfg(SCEW),
|
||||
mc_make_sid_security_cfg(AFIR),
|
||||
mc_make_sid_security_cfg(NVDISPLAYR1),
|
||||
mc_make_sid_security_cfg(XUSB_DEVR),
|
||||
mc_make_sid_security_cfg(VICSRD1),
|
||||
mc_make_sid_security_cfg(NVENCSWR),
|
||||
mc_make_sid_security_cfg(TSECSRDB),
|
||||
mc_make_sid_security_cfg(AXISW),
|
||||
mc_make_sid_security_cfg(SDMMCWAB),
|
||||
mc_make_sid_security_cfg(AONDMAW),
|
||||
mc_make_sid_security_cfg(GPUSWR2),
|
||||
mc_make_sid_security_cfg(SATAW),
|
||||
mc_make_sid_security_cfg(UFSHCW),
|
||||
mc_make_sid_security_cfg(AFIW),
|
||||
mc_make_sid_security_cfg(SDMMCR),
|
||||
mc_make_sid_security_cfg(SCEDMAW),
|
||||
mc_make_sid_security_cfg(UFSHCR),
|
||||
mc_make_sid_security_cfg(SDMMCWAA),
|
||||
mc_make_sid_security_cfg(APEDMAW),
|
||||
mc_make_sid_security_cfg(SESWR),
|
||||
mc_make_sid_security_cfg(MPCORER),
|
||||
mc_make_sid_security_cfg(PTCR),
|
||||
mc_make_sid_security_cfg(BPMPW),
|
||||
mc_make_sid_security_cfg(ETRW),
|
||||
mc_make_sid_security_cfg(GPUSRD),
|
||||
mc_make_sid_security_cfg(VICSWR),
|
||||
mc_make_sid_security_cfg(SCEDMAR),
|
||||
mc_make_sid_security_cfg(HDAW),
|
||||
mc_make_sid_security_cfg(ISPWA),
|
||||
mc_make_sid_security_cfg(EQOSW),
|
||||
mc_make_sid_security_cfg(XUSB_HOSTW),
|
||||
mc_make_sid_security_cfg(TSECSWR),
|
||||
mc_make_sid_security_cfg(SDMMCRAA),
|
||||
mc_make_sid_security_cfg(APER),
|
||||
mc_make_sid_security_cfg(VIW),
|
||||
mc_make_sid_security_cfg(APEW),
|
||||
mc_make_sid_security_cfg(AXISR),
|
||||
mc_make_sid_security_cfg(SDMMCW),
|
||||
mc_make_sid_security_cfg(BPMPDMAW),
|
||||
mc_make_sid_security_cfg(ISPRA),
|
||||
mc_make_sid_security_cfg(NVDECSWR),
|
||||
mc_make_sid_security_cfg(XUSB_DEVW),
|
||||
mc_make_sid_security_cfg(NVDECSRD),
|
||||
mc_make_sid_security_cfg(MPCOREW),
|
||||
mc_make_sid_security_cfg(NVDISPLAYR),
|
||||
mc_make_sid_security_cfg(BPMPDMAR),
|
||||
mc_make_sid_security_cfg(NVJPGSWR),
|
||||
mc_make_sid_security_cfg(NVDECSRD1),
|
||||
mc_make_sid_security_cfg(TSECSRD),
|
||||
mc_make_sid_security_cfg(NVJPGSRD),
|
||||
mc_make_sid_security_cfg(SDMMCWA),
|
||||
mc_make_sid_security_cfg(SCER),
|
||||
mc_make_sid_security_cfg(XUSB_HOSTR),
|
||||
mc_make_sid_security_cfg(VICSRD),
|
||||
mc_make_sid_security_cfg(AONDMAR),
|
||||
mc_make_sid_security_cfg(AONW),
|
||||
mc_make_sid_security_cfg(SDMMCRA),
|
||||
mc_make_sid_security_cfg(HOST1XDMAR),
|
||||
mc_make_sid_security_cfg(EQOSR),
|
||||
mc_make_sid_security_cfg(SATAR),
|
||||
mc_make_sid_security_cfg(BPMPR),
|
||||
mc_make_sid_security_cfg(HDAR),
|
||||
mc_make_sid_security_cfg(SDMMCRAB),
|
||||
mc_make_sid_security_cfg(ETRR),
|
||||
mc_make_sid_security_cfg(AONR),
|
||||
mc_make_sid_security_cfg(APEDMAR),
|
||||
mc_make_sid_security_cfg(SESRD),
|
||||
mc_make_sid_security_cfg(NVENCSRD),
|
||||
mc_make_sid_security_cfg(GPUSWR),
|
||||
mc_make_sid_security_cfg(TSECSWRB),
|
||||
mc_make_sid_security_cfg(ISPWB),
|
||||
mc_make_sid_security_cfg(GPUSRD2),
|
||||
mc_make_sid_override_cfg(APER),
|
||||
mc_make_sid_override_cfg(VICSRD),
|
||||
mc_make_sid_override_cfg(NVENCSRD),
|
||||
mc_make_sid_override_cfg(NVJPGSWR),
|
||||
mc_make_sid_override_cfg(AONW),
|
||||
mc_make_sid_override_cfg(BPMPR),
|
||||
mc_make_sid_override_cfg(BPMPW),
|
||||
mc_make_sid_override_cfg(HDAW),
|
||||
mc_make_sid_override_cfg(NVDISPLAYR1),
|
||||
mc_make_sid_override_cfg(APEDMAR),
|
||||
mc_make_sid_override_cfg(AFIR),
|
||||
mc_make_sid_override_cfg(AXISR),
|
||||
mc_make_sid_override_cfg(VICSRD1),
|
||||
mc_make_sid_override_cfg(TSECSRD),
|
||||
mc_make_sid_override_cfg(BPMPDMAW),
|
||||
mc_make_sid_override_cfg(MPCOREW),
|
||||
mc_make_sid_override_cfg(XUSB_HOSTR),
|
||||
mc_make_sid_override_cfg(GPUSWR),
|
||||
mc_make_sid_override_cfg(XUSB_DEVR),
|
||||
mc_make_sid_override_cfg(UFSHCW),
|
||||
mc_make_sid_override_cfg(XUSB_HOSTW),
|
||||
mc_make_sid_override_cfg(SDMMCWAB),
|
||||
mc_make_sid_override_cfg(SATAW),
|
||||
mc_make_sid_override_cfg(SCEDMAR),
|
||||
mc_make_sid_override_cfg(HOST1XDMAR),
|
||||
mc_make_sid_override_cfg(SDMMCWA),
|
||||
mc_make_sid_override_cfg(APEDMAW),
|
||||
mc_make_sid_override_cfg(SESWR),
|
||||
mc_make_sid_override_cfg(AXISW),
|
||||
mc_make_sid_override_cfg(AONDMAW),
|
||||
mc_make_sid_override_cfg(TSECSWRB),
|
||||
mc_make_sid_override_cfg(MPCORER),
|
||||
mc_make_sid_override_cfg(ISPWB),
|
||||
mc_make_sid_override_cfg(AONR),
|
||||
mc_make_sid_override_cfg(BPMPDMAR),
|
||||
mc_make_sid_override_cfg(HDAR),
|
||||
mc_make_sid_override_cfg(SDMMCRA),
|
||||
mc_make_sid_override_cfg(ETRW),
|
||||
mc_make_sid_override_cfg(GPUSWR2),
|
||||
mc_make_sid_override_cfg(EQOSR),
|
||||
mc_make_sid_override_cfg(TSECSWR),
|
||||
mc_make_sid_override_cfg(ETRR),
|
||||
mc_make_sid_override_cfg(NVDECSRD),
|
||||
mc_make_sid_override_cfg(TSECSRDB),
|
||||
mc_make_sid_override_cfg(SDMMCRAA),
|
||||
mc_make_sid_override_cfg(NVDECSRD1),
|
||||
mc_make_sid_override_cfg(SDMMCR),
|
||||
mc_make_sid_override_cfg(NVJPGSRD),
|
||||
mc_make_sid_override_cfg(SCEDMAW),
|
||||
mc_make_sid_override_cfg(SDMMCWAA),
|
||||
mc_make_sid_override_cfg(APEW),
|
||||
mc_make_sid_override_cfg(AONDMAR),
|
||||
mc_make_sid_override_cfg(PTCR),
|
||||
mc_make_sid_override_cfg(SCER),
|
||||
mc_make_sid_override_cfg(ISPRA),
|
||||
mc_make_sid_override_cfg(ISPWA),
|
||||
mc_make_sid_override_cfg(VICSWR),
|
||||
mc_make_sid_override_cfg(SESRD),
|
||||
mc_make_sid_override_cfg(SDMMCW),
|
||||
mc_make_sid_override_cfg(SDMMCRAB),
|
||||
mc_make_sid_override_cfg(EQOSW),
|
||||
mc_make_sid_override_cfg(GPUSRD2),
|
||||
mc_make_sid_override_cfg(SCEW),
|
||||
mc_make_sid_override_cfg(GPUSRD),
|
||||
mc_make_sid_override_cfg(NVDECSWR),
|
||||
mc_make_sid_override_cfg(XUSB_DEVW),
|
||||
mc_make_sid_override_cfg(SATAR),
|
||||
mc_make_sid_override_cfg(NVDISPLAYR),
|
||||
mc_make_sid_override_cfg(VIW),
|
||||
mc_make_sid_override_cfg(UFSHCR),
|
||||
mc_make_sid_override_cfg(NVENCSWR),
|
||||
mc_make_sid_override_cfg(AFIW),
|
||||
smmu_make_gnsr0_nsec_cfg(CR0),
|
||||
smmu_make_gnsr0_sec_cfg(IDR0),
|
||||
smmu_make_gnsr0_sec_cfg(IDR1),
|
||||
smmu_make_gnsr0_sec_cfg(IDR2),
|
||||
smmu_make_gnsr0_nsec_cfg(GFSR),
|
||||
smmu_make_gnsr0_nsec_cfg(GFSYNR0),
|
||||
smmu_make_gnsr0_nsec_cfg(GFSYNR1),
|
||||
smmu_make_gnsr0_nsec_cfg(TLBGSTATUS),
|
||||
smmu_make_gnsr0_nsec_cfg(PIDR2),
|
||||
smmu_make_smrg_group(0),
|
||||
smmu_make_smrg_group(1),
|
||||
smmu_make_smrg_group(2),
|
||||
smmu_make_smrg_group(3),
|
||||
smmu_make_smrg_group(4),
|
||||
smmu_make_smrg_group(5),
|
||||
smmu_make_smrg_group(6),
|
||||
smmu_make_smrg_group(7),
|
||||
smmu_make_smrg_group(8),
|
||||
smmu_make_smrg_group(9),
|
||||
smmu_make_smrg_group(10),
|
||||
smmu_make_smrg_group(11),
|
||||
smmu_make_smrg_group(12),
|
||||
smmu_make_smrg_group(13),
|
||||
smmu_make_smrg_group(14),
|
||||
smmu_make_smrg_group(15),
|
||||
smmu_make_smrg_group(16),
|
||||
smmu_make_smrg_group(17),
|
||||
smmu_make_smrg_group(18),
|
||||
smmu_make_smrg_group(19),
|
||||
smmu_make_smrg_group(20),
|
||||
smmu_make_smrg_group(21),
|
||||
smmu_make_smrg_group(22),
|
||||
smmu_make_smrg_group(23),
|
||||
smmu_make_smrg_group(24),
|
||||
smmu_make_smrg_group(25),
|
||||
smmu_make_smrg_group(26),
|
||||
smmu_make_smrg_group(27),
|
||||
smmu_make_smrg_group(28),
|
||||
smmu_make_smrg_group(29),
|
||||
smmu_make_smrg_group(30),
|
||||
smmu_make_smrg_group(31),
|
||||
smmu_make_smrg_group(32),
|
||||
smmu_make_smrg_group(33),
|
||||
smmu_make_smrg_group(34),
|
||||
smmu_make_smrg_group(35),
|
||||
smmu_make_smrg_group(36),
|
||||
smmu_make_smrg_group(37),
|
||||
smmu_make_smrg_group(38),
|
||||
smmu_make_smrg_group(39),
|
||||
smmu_make_smrg_group(40),
|
||||
smmu_make_smrg_group(41),
|
||||
smmu_make_smrg_group(42),
|
||||
smmu_make_smrg_group(43),
|
||||
smmu_make_smrg_group(44),
|
||||
smmu_make_smrg_group(45),
|
||||
smmu_make_smrg_group(46),
|
||||
smmu_make_smrg_group(47),
|
||||
smmu_make_smrg_group(48),
|
||||
smmu_make_smrg_group(49),
|
||||
smmu_make_smrg_group(50),
|
||||
smmu_make_smrg_group(51),
|
||||
smmu_make_smrg_group(52),
|
||||
smmu_make_smrg_group(53),
|
||||
smmu_make_smrg_group(54),
|
||||
smmu_make_smrg_group(55),
|
||||
smmu_make_smrg_group(56),
|
||||
smmu_make_smrg_group(57),
|
||||
smmu_make_smrg_group(58),
|
||||
smmu_make_smrg_group(59),
|
||||
smmu_make_smrg_group(60),
|
||||
smmu_make_smrg_group(61),
|
||||
smmu_make_smrg_group(62),
|
||||
smmu_make_smrg_group(63),
|
||||
smmu_make_cb_group(0),
|
||||
smmu_make_cb_group(1),
|
||||
smmu_make_cb_group(2),
|
||||
smmu_make_cb_group(3),
|
||||
smmu_make_cb_group(4),
|
||||
smmu_make_cb_group(5),
|
||||
smmu_make_cb_group(6),
|
||||
smmu_make_cb_group(7),
|
||||
smmu_make_cb_group(8),
|
||||
smmu_make_cb_group(9),
|
||||
smmu_make_cb_group(10),
|
||||
smmu_make_cb_group(11),
|
||||
smmu_make_cb_group(12),
|
||||
smmu_make_cb_group(13),
|
||||
smmu_make_cb_group(14),
|
||||
smmu_make_cb_group(15),
|
||||
smmu_make_cb_group(16),
|
||||
smmu_make_cb_group(17),
|
||||
smmu_make_cb_group(18),
|
||||
smmu_make_cb_group(19),
|
||||
smmu_make_cb_group(20),
|
||||
smmu_make_cb_group(21),
|
||||
smmu_make_cb_group(22),
|
||||
smmu_make_cb_group(23),
|
||||
smmu_make_cb_group(24),
|
||||
smmu_make_cb_group(25),
|
||||
smmu_make_cb_group(26),
|
||||
smmu_make_cb_group(27),
|
||||
smmu_make_cb_group(28),
|
||||
smmu_make_cb_group(29),
|
||||
smmu_make_cb_group(30),
|
||||
smmu_make_cb_group(31),
|
||||
smmu_make_cb_group(32),
|
||||
smmu_make_cb_group(33),
|
||||
smmu_make_cb_group(34),
|
||||
smmu_make_cb_group(35),
|
||||
smmu_make_cb_group(36),
|
||||
smmu_make_cb_group(37),
|
||||
smmu_make_cb_group(38),
|
||||
smmu_make_cb_group(39),
|
||||
smmu_make_cb_group(40),
|
||||
smmu_make_cb_group(41),
|
||||
smmu_make_cb_group(42),
|
||||
smmu_make_cb_group(43),
|
||||
smmu_make_cb_group(44),
|
||||
smmu_make_cb_group(45),
|
||||
smmu_make_cb_group(46),
|
||||
smmu_make_cb_group(47),
|
||||
smmu_make_cb_group(48),
|
||||
smmu_make_cb_group(49),
|
||||
smmu_make_cb_group(50),
|
||||
smmu_make_cb_group(51),
|
||||
smmu_make_cb_group(52),
|
||||
smmu_make_cb_group(53),
|
||||
smmu_make_cb_group(54),
|
||||
smmu_make_cb_group(55),
|
||||
smmu_make_cb_group(56),
|
||||
smmu_make_cb_group(57),
|
||||
smmu_make_cb_group(58),
|
||||
smmu_make_cb_group(59),
|
||||
smmu_make_cb_group(60),
|
||||
smmu_make_cb_group(61),
|
||||
smmu_make_cb_group(62),
|
||||
smmu_make_cb_group(63),
|
||||
smmu_bypass_cfg, /* TBU settings */
|
||||
_END_OF_TABLE_,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
* Handler to return the pointer to the SMMU's context struct
|
||||
******************************************************************************/
|
||||
smmu_regs_t *plat_get_smmu_ctx(void)
|
||||
{
|
||||
/* index of _END_OF_TABLE_ */
|
||||
tegra186_smmu_context[0].val = ARRAY_SIZE(tegra186_smmu_context) - 1;
|
||||
|
||||
return tegra186_smmu_context;
|
||||
}
|
|
@ -71,7 +71,7 @@ PLAT_INCLUDES += -I${SOC_DIR}/drivers/include
|
|||
|
||||
BL31_SOURCES += lib/cpus/aarch64/denver.S \
|
||||
lib/cpus/aarch64/cortex_a57.S \
|
||||
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
|
||||
${COMMON_DIR}/drivers/memctrl/memctrl_v2.c \
|
||||
${COMMON_DIR}/drivers/smmu/smmu.c \
|
||||
${SOC_DIR}/drivers/mce/mce.c \
|
||||
${SOC_DIR}/drivers/mce/ari.c \
|
||||
|
@ -82,5 +82,6 @@ BL31_SOURCES += lib/cpus/aarch64/denver.S \
|
|||
${SOC_DIR}/plat_setup.c \
|
||||
${SOC_DIR}/plat_secondary.c \
|
||||
${SOC_DIR}/plat_sip_calls.c \
|
||||
${SOC_DIR}/plat_smmu.c \
|
||||
${SOC_DIR}/plat_trampoline.S
|
||||
|
||||
|
|
Loading…
Reference in New Issue