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rockchip: support rk3399 gpio driver 

There are 5 groups of GPIO (GPIO0~GPIO4), totally have 122 GPIOs
on rk3399 platform.
The pull direction(pullup or pulldown) for all of GPIOs are
software-programmable.
At the moment, we add the gpio basic driver since reset or power off
the devices from gpio configuration for BL31.
This commit is contained in:
Caesar Wang 2016-05-25 19:21:43 +08:00
parent 195889829e
commit 9901dcf6bb
7 changed files with 274 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
plat/rockchip/common/include/plat_private.h
View File

@ -110,6 +110,8 @@ void plat_setup_rockchip_pm_ops(struct rockchip_pm_ops_cb *ops);
void platform_cpu_warmboot(void);
void plat_rockchip_gpio_init(void);
extern const unsigned char rockchip_power_domain_tree_desc[];
extern void *pmu_cpuson_entrypoint_start;

227
plat/rockchip/rk3399/drivers/gpio/rk3399_gpio.c Normal file
View File

@ -0,0 +1,227 @@
/*
* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
*
* Redistributions of source code must retain the above copyright notice, this
* list of conditions and the following disclaimer.
*
* Redistributions in binary form must reproduce the above copyright notice,
* this list of conditions and the following disclaimer in the documentation
* and/or other materials provided with the distribution.
*
* Neither the name of ARM nor the names of its contributors may be used
* to endorse or promote products derived from this software without specific
* prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
* POSSIBILITY OF SUCH DAMAGE.
*/
#include <assert.h>
#include <debug.h>
#include <delay_timer.h>
#include <errno.h>
#include <gpio.h>
#include <mmio.h>
#include <platform.h>
#include <platform_def.h>
#include <plat_private.h>
#include <soc.h>
uint32_t gpio_port[] = {
GPIO0_BASE,
GPIO1_BASE,
GPIO2_BASE,
GPIO3_BASE,
GPIO4_BASE,
};
#define SWPORTA_DR 0x00
#define SWPORTA_DDR 0x04
#define EXT_PORTA 0x50
#define PMU_GPIO_PORT0 0
#define PMU_GPIO_PORT1 1
#define PMU_GRF_GPIO0A_P 0x40
#define GRF_GPIO2A_P 0xe040
#define GPIO_P_MASK 0x03
/*
* gpio clock disabled when not operate
* so need to enable gpio clock before operate gpio
* after setting, need to disable gpio clock
* gate 1: disable clock; 0: enable clock
*/
static void gpio_clk(int gpio, uint32_t gate)
{
uint32_t port = gpio / 32;
assert(port < 5);
switch (port) {
case 0:
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
BITS_WITH_WMASK(gate, CLK_GATE_MASK,
PCLK_GPIO0_GATE_SHIFT));
break;
case 1:
mmio_write_32(PMUCRU_BASE + CRU_PMU_CLKGATE_CON(1),
BITS_WITH_WMASK(gate, CLK_GATE_MASK,
PCLK_GPIO1_GATE_SHIFT));
break;
case 2:
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
BITS_WITH_WMASK(gate, CLK_GATE_MASK,
PCLK_GPIO2_GATE_SHIFT));
break;
case 3:
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
BITS_WITH_WMASK(gate, CLK_GATE_MASK,
PCLK_GPIO3_GATE_SHIFT));
break;
case 4:
mmio_write_32(CRU_BASE + CRU_CLKGATE_CON(31),
BITS_WITH_WMASK(gate, CLK_GATE_MASK,
PCLK_GPIO4_GATE_SHIFT));
break;
default:
break;
}
}
static void set_pull(int gpio, int pull)
{
uint32_t port = gpio / 32;
uint32_t num = gpio % 32;
uint32_t bank = num / 8;
uint32_t id = num % 8;
assert((port < 5) && (num < 32));
gpio_clk(gpio, 0);
/*
* in gpio0a, gpio0b, gpio2c, gpio2d,
* 00: Z
* 01: pull down
* 10: Z
* 11: pull up
* different with other gpio, so need to correct it
*/
if (((port == 0) && (bank < 2)) || ((port == 2) && (bank > 2))) {
if (pull == GPIO_PULL_UP)
pull = 3;
else if (pull == GPIO_PULL_DOWN)
pull = 1;
else
pull = 0;
}
if (port == PMU_GPIO_PORT0 || port == PMU_GPIO_PORT1) {
mmio_write_32(PMUGRF_BASE + PMU_GRF_GPIO0A_P +
port * 16 + bank * 4,
BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2));
} else {
mmio_write_32(GRF_BASE + GRF_GPIO2A_P +
(port - 2) * 16 + bank * 4,
BITS_WITH_WMASK(pull, GPIO_P_MASK, id * 2));
}
gpio_clk(gpio, 1);
}
static void set_direction(int gpio, int direction)
{
uint32_t port = gpio / 32;
uint32_t num = gpio % 32;
assert((port < 5) && (num < 32));
gpio_clk(gpio, 0);
/*
* in gpio.h
* #define GPIO_DIR_OUT 0
* #define GPIO_DIR_IN 1
* but rk3399 gpio direction 1: output, 0: input
* so need to revert direction value
*/
mmio_setbits_32(gpio_port[port] + SWPORTA_DDR, !direction << num);
gpio_clk(gpio, 1);
}
static int get_direction(int gpio)
{
uint32_t port = gpio / 32;
uint32_t num = gpio % 32;
int direction;
assert((port < 5) && (num < 32));
gpio_clk(gpio, 0);
/*
* in gpio.h
* #define GPIO_DIR_OUT 0
* #define GPIO_DIR_IN 1
* but rk3399 gpio direction 1: output, 0: input
* so need to revert direction value
*/
direction = !((mmio_read_32(gpio_port[port] +
SWPORTA_DDR) >> num) & 0x1);
gpio_clk(gpio, 1);
return direction;
}
static int get_value(int gpio)
{
uint32_t port = gpio / 32;
uint32_t num = gpio % 32;
int value;
assert((port < 5) && (num < 32));
gpio_clk(gpio, 0);
value = (mmio_read_32(gpio_port[port] + EXT_PORTA) >> num) & 0x1;
gpio_clk(gpio, 1);
return value;
}
static void set_value(int gpio, int value)
{
uint32_t port = gpio / 32;
uint32_t num = gpio % 32;
assert((port < 5) && (num < 32));
gpio_clk(gpio, 0);
mmio_clrsetbits_32(gpio_port[port] + SWPORTA_DR, 1 << num,
!!value << num);
gpio_clk(gpio, 0);
}
const gpio_ops_t rk3399_gpio_ops = {
.get_direction = get_direction,
.set_direction = set_direction,
.get_value = get_value,
.set_value = set_value,
.set_pull = set_pull,
};
void plat_rockchip_gpio_init(void)
{
gpio_init(&rk3399_gpio_ops);
}

14
plat/rockchip/rk3399/drivers/soc/soc.c
View File

@ -57,7 +57,18 @@ const mmap_region_t plat_rk_mmap[] = {
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(PMUGRF_BASE, PMUGRF_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GPIO0_BASE, GPIO0_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GPIO1_BASE, GPIO1_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GPIO2_BASE, GPIO2_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GPIO3_BASE, GPIO3_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GPIO4_BASE, GPIO4_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
MAP_REGION_FLAT(GRF_BASE, GRF_SIZE,
MT_DEVICE | MT_RW | MT_SECURE),
{ 0 }
};
@ -349,4 +360,5 @@ void plat_rockchip_soc_init(void)
dma_secure_cfg(0);
sgrf_init();
soc_global_soft_reset_init();
plat_rockchip_gpio_init();
}

11
plat/rockchip/rk3399/drivers/soc/soc.h
View File

@ -72,6 +72,8 @@
#define REG_SIZE 0x04
#define REG_SOC_WMSK 0xffff0000
#define CLK_GATE_MASK 0x01
enum plls_id {
ALPLL_ID = 0,
ABPLL_ID,
@ -152,6 +154,11 @@ struct deepsleep_data_s {
#define CRU_GLB_SRST_FST 0x0500
#define CRU_GLB_SRST_SND 0x0504
#define CRU_CLKGATE_CON(n) (0x300 + n * 4)
#define PCLK_GPIO2_GATE_SHIFT 3
#define PCLK_GPIO3_GATE_SHIFT 4
#define PCLK_GPIO4_GATE_SHIFT 5
/**************************************************
* pmu cru reg, offset
**************************************************/
@ -167,6 +174,10 @@ struct deepsleep_data_s {
#define CRU_PMU_FIRST_SFTRST_MSK (0x3 << 2)
#define CRU_PMU_FIRST_SFTRST_EN 0x0
#define CRU_PMU_CLKGATE_CON(n) (0x100 + n * 4)
#define PCLK_GPIO0_GATE_SHIFT 3
#define PCLK_GPIO1_GATE_SHIFT 4
/**************************************************
* sgrf reg, offset
**************************************************/

2
plat/rockchip/rk3399/include/platform_def.h
View File

@ -109,7 +109,7 @@
******************************************************************************/
#define ADDR_SPACE_SIZE (1ull << 32)
#define MAX_XLAT_TABLES 20
#define MAX_MMAP_REGIONS 16
#define MAX_MMAP_REGIONS 20
/*******************************************************************************
* Declarations and constants to access the mailboxes safely. Each mailbox is

2
plat/rockchip/rk3399/platform.mk
View File

@ -58,6 +58,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
drivers/ti/uart/16550_console.S \
drivers/delay_timer/delay_timer.c \
drivers/delay_timer/generic_delay_timer.c \
drivers/gpio/gpio.c \
lib/cpus/aarch64/cortex_a53.S \
lib/cpus/aarch64/cortex_a72.S \
plat/common/aarch64/platform_mp_stack.S \
@ -68,6 +69,7 @@ BL31_SOURCES += ${RK_GIC_SOURCES}
${RK_PLAT_COMMON}/plat_pm.c \
${RK_PLAT_COMMON}/plat_topology.c \
${RK_PLAT_COMMON}/aarch64/platform_common.c \
${RK_PLAT_SOC}/drivers/gpio/rk3399_gpio.c \
${RK_PLAT_SOC}/drivers/pmu/pmu.c \
${RK_PLAT_SOC}/drivers/soc/soc.c

18
plat/rockchip/rk3399/rk3399_def.h
View File

@ -64,6 +64,24 @@
#define PMUGRF_BASE 0xff320000
#define PMUGRF_SIZE SIZE_K(64)
#define GPIO0_BASE 0xff720000
#define GPIO0_SIZE SIZE_K(64)
#define GPIO1_BASE 0xff730000
#define GPIO1_SIZE SIZE_K(64)
#define GPIO2_BASE 0xff780000
#define GPIO2_SIZE SIZE_K(32)
#define GPIO3_BASE 0xff788000
#define GPIO3_SIZE SIZE_K(32)
#define GPIO4_BASE 0xff790000
#define GPIO4_SIZE SIZE_K(32)
#define GRF_BASE 0xff770000
#define GRF_SIZE SIZE_K(64)
/*
* include i2c pmu/audio, pwm0-3 rkpwm0-3 uart_dbg,mailbox scr
* 0xff650000 -0xff6c0000