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Merge changes from topic "rockchip-uart-fixes" into integration 

* changes:
  rockchip: rk3399: store actual debug uart information on suspend
  rockchip: move dt-coreboot uart distinction into param handling code
  rockchip: make uart baudrate configurable
  rockchip: px30: add uart5 as option for serial output
This commit is contained in:
Paul Beesley 2019-08-15 15:30:13 +00:00 committed by TrustedFirmware Code Review
parent 585df3b49b 0eb7fa91e1
commit 99becbe3df
6 changed files with 101 additions and 46 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

15
plat/rockchip/common/bl31_plat_setup.c
View File

@ -14,7 +14,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@ -62,16 +61,10 @@ void bl31_early_platform_setup2(u_register_t arg0, u_register_t arg1,
params_early_setup(arg1);
#if COREBOOT
if (coreboot_serial.type)
console_16550_register(coreboot_serial.baseaddr,
coreboot_serial.input_hertz,
coreboot_serial.baud,
&console);
#else
console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
PLAT_RK_UART_BAUDRATE, &console);
#endif
if (rockchip_get_uart_base() != 0)
console_16550_register(rockchip_get_uart_base(),
rockchip_get_uart_clock(),
rockchip_get_uart_baudrate(), &console);
VERBOSE("bl31_setup\n");

2
plat/rockchip/common/include/plat_private.h
View File

@ -139,6 +139,8 @@ extern uint32_t cpuson_flags[PLATFORM_CORE_COUNT];
extern const mmap_region_t plat_rk_mmap[];
uint32_t rockchip_get_uart_base(void);
uint32_t rockchip_get_uart_baudrate(void);
uint32_t rockchip_get_uart_clock(void);
#endif /* __ASSEMBLER__ */

68
plat/rockchip/common/params_setup.c
View File

@ -26,12 +26,6 @@ static struct bl_aux_gpio_info poweroff_gpio;
static struct bl_aux_gpio_info suspend_gpio[10];
uint32_t suspend_gpio_cnt;
static struct bl_aux_rk_apio_info suspend_apio;
static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
uint32_t rockchip_get_uart_base(void)
{
return rk_uart_base;
}
#if COREBOOT
static int dt_process_fdt(u_register_t param_from_bl2)
@ -39,6 +33,9 @@ static int dt_process_fdt(u_register_t param_from_bl2)
return -ENODEV;
}
#else
static uint32_t rk_uart_base = PLAT_RK_UART_BASE;
static uint32_t rk_uart_baudrate = PLAT_RK_UART_BAUDRATE;
static uint32_t rk_uart_clock = PLAT_RK_UART_CLOCK;
static uint8_t fdt_buffer[0x10000];
void *plat_get_fdt(void)
@ -53,9 +50,12 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
int node_offset;
int stdout_path_len;
const char *stdout_path;
const char *separator;
const char *baud_start;
char serial_char;
int serial_no;
uint32_t uart_base;
uint32_t baud;
node_offset = fdt_path_offset(fdt, path_name);
if (node_offset < 0)
@ -68,7 +68,7 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
/*
* We expect something like:
* "serial0:...""
* "serial0:baudrate"
*/
if (strncmp("serial", stdout_path, 6) != 0)
return;
@ -95,12 +95,39 @@ static void plat_rockchip_dt_process_fdt_uart(void *fdt)
case 4:
uart_base = UART4_BASE;
break;
#endif
#ifdef UART5_BASE
case 5:
uart_base = UART5_BASE;
break;
#endif
default:
return;
}
rk_uart_base = uart_base;
separator = strchr(stdout_path, ':');
if (!separator)
return;
baud = 0;
baud_start = separator + 1;
while (*baud_start != '\0') {
/*
* uart binding is <baud>{<parity>{<bits>{...}}}
* So the baudrate either is the whole string, or
* we end in the parity characters.
*/
if (*baud_start == 'n' || *baud_start == 'o' ||
*baud_start == 'e')
break;
baud = baud * 10 + (*baud_start - '0');
baud_start++;
}
rk_uart_baudrate = baud;
}
static int dt_process_fdt(u_register_t param_from_bl2)
@ -118,6 +145,33 @@ static int dt_process_fdt(u_register_t param_from_bl2)
}
#endif
uint32_t rockchip_get_uart_base(void)
{
#if COREBOOT
return coreboot_serial.baseaddr;
#else
return rk_uart_base;
#endif
}
uint32_t rockchip_get_uart_baudrate(void)
{
#if COREBOOT
return coreboot_serial.baud;
#else
return rk_uart_baudrate;
#endif
}
uint32_t rockchip_get_uart_clock(void)
{
#if COREBOOT
return coreboot_serial.input_hertz;
#else
return rk_uart_clock;
#endif
}
struct bl_aux_gpio_info *plat_get_rockchip_gpio_reset(void)
{
return &rst_gpio;

16
plat/rockchip/common/sp_min_plat_setup.c
View File

@ -15,7 +15,6 @@
#include <drivers/console.h>
#include <drivers/generic_delay_timer.h>
#include <drivers/ti/uart/uart_16550.h>
#include <lib/coreboot.h>
#include <lib/mmio.h>
#include <plat_private.h>
#include <plat/common/platform.h>
@ -57,16 +56,11 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
params_early_setup(arg1);
#if COREBOOT
if (coreboot_serial.type)
console_16550_register(coreboot_serial.baseaddr,
coreboot_serial.input_hertz,
coreboot_serial.baud,
&console);
#else
console_16550_register(rockchip_get_uart_base(), PLAT_RK_UART_CLOCK,
PLAT_RK_UART_BAUDRATE, &console);
#endif
if (rockchip_get_uart_base() != 0)
console_16550_register(rockchip_get_uart_base(),
rockchip_get_uart_clock(),
rockchip_get_uart_baudrate(), &console);
VERBOSE("sp_min_setup\n");
bl31_params_parse_helper(arg0, NULL, &bl33_ep_info);

3
plat/rockchip/px30/px30_def.h
View File

@ -54,6 +54,9 @@
#define UART2_BASE 0xff160000
#define UART2_SIZE SIZE_K(64)
#define UART5_BASE 0xff178000
#define UART5_SIZE SIZE_K(64)
#define I2C0_BASE 0xff180000
#define I2C0_SIZE SIZE_K(64)

43
plat/rockchip/rk3399/drivers/pmu/pmu.c
View File

@ -1125,32 +1125,41 @@ static struct uart_debug uart_save;
void suspend_uart(void)
{
uart_save.uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
uart_save.uart_ier = mmio_read_32(PLAT_RK_UART_BASE + UART_IER);
uart_save.uart_mcr = mmio_read_32(PLAT_RK_UART_BASE + UART_MCR);
mmio_write_32(PLAT_RK_UART_BASE + UART_LCR,
uint32_t uart_base = rockchip_get_uart_base();
if (uart_base == 0)
return;
uart_save.uart_lcr = mmio_read_32(uart_base + UART_LCR);
uart_save.uart_ier = mmio_read_32(uart_base + UART_IER);
uart_save.uart_mcr = mmio_read_32(uart_base + UART_MCR);
mmio_write_32(uart_base + UART_LCR,
uart_save.uart_lcr | UARTLCR_DLAB);
uart_save.uart_dll = mmio_read_32(PLAT_RK_UART_BASE + UART_DLL);
uart_save.uart_dlh = mmio_read_32(PLAT_RK_UART_BASE + UART_DLH);
mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
uart_save.uart_dll = mmio_read_32(uart_base + UART_DLL);
uart_save.uart_dlh = mmio_read_32(uart_base + UART_DLH);
mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
}
void resume_uart(void)
{
uint32_t uart_base = rockchip_get_uart_base();
uint32_t uart_lcr;
mmio_write_32(PLAT_RK_UART_BASE + UARTSRR,
if (uart_base == 0)
return;
mmio_write_32(uart_base + UARTSRR,
XMIT_FIFO_RESET | RCVR_FIFO_RESET | UART_RESET);
uart_lcr = mmio_read_32(PLAT_RK_UART_BASE + UART_LCR);
mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, DIAGNOSTIC_MODE);
mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_lcr | UARTLCR_DLAB);
mmio_write_32(PLAT_RK_UART_BASE + UART_DLL, uart_save.uart_dll);
mmio_write_32(PLAT_RK_UART_BASE + UART_DLH, uart_save.uart_dlh);
mmio_write_32(PLAT_RK_UART_BASE + UART_LCR, uart_save.uart_lcr);
mmio_write_32(PLAT_RK_UART_BASE + UART_IER, uart_save.uart_ier);
mmio_write_32(PLAT_RK_UART_BASE + UART_FCR, UARTFCR_FIFOEN);
mmio_write_32(PLAT_RK_UART_BASE + UART_MCR, uart_save.uart_mcr);
uart_lcr = mmio_read_32(uart_base + UART_LCR);
mmio_write_32(uart_base + UART_MCR, DIAGNOSTIC_MODE);
mmio_write_32(uart_base + UART_LCR, uart_lcr | UARTLCR_DLAB);
mmio_write_32(uart_base + UART_DLL, uart_save.uart_dll);
mmio_write_32(uart_base + UART_DLH, uart_save.uart_dlh);
mmio_write_32(uart_base + UART_LCR, uart_save.uart_lcr);
mmio_write_32(uart_base + UART_IER, uart_save.uart_ier);
mmio_write_32(uart_base + UART_FCR, UARTFCR_FIFOEN);
mmio_write_32(uart_base + UART_MCR, uart_save.uart_mcr);
}
void save_usbphy(void)