Merge pull request #695 from soby-mathew/sm/AArch32_fixes
Fixes for AArch32 port of TF
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commit
99e89377eb
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@ -419,9 +419,11 @@ void print_entry_point_info(const entry_point_info_t *ep_info)
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PRINT_IMAGE_ARG(1);
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PRINT_IMAGE_ARG(1);
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PRINT_IMAGE_ARG(2);
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PRINT_IMAGE_ARG(2);
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PRINT_IMAGE_ARG(3);
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PRINT_IMAGE_ARG(3);
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#ifndef AARCH32
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PRINT_IMAGE_ARG(4);
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PRINT_IMAGE_ARG(4);
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PRINT_IMAGE_ARG(5);
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PRINT_IMAGE_ARG(5);
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PRINT_IMAGE_ARG(6);
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PRINT_IMAGE_ARG(6);
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PRINT_IMAGE_ARG(7);
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PRINT_IMAGE_ARG(7);
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#endif
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#undef PRINT_IMAGE_ARG
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#undef PRINT_IMAGE_ARG
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}
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}
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@ -86,6 +86,8 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t
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/* Clear any residual register values from the context */
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/* Clear any residual register values from the context */
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memset(ctx, 0, sizeof(*ctx));
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memset(ctx, 0, sizeof(*ctx));
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reg_ctx = get_regs_ctx(ctx);
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/*
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/*
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* Base the context SCR on the current value, adjust for entry point
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* Base the context SCR on the current value, adjust for entry point
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* specific requirements
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* specific requirements
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@ -121,8 +123,6 @@ static void cm_init_context_common(cpu_context_t *ctx, const entry_point_info_t
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if (GET_M32(ep->spsr) == MODE32_hyp)
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if (GET_M32(ep->spsr) == MODE32_hyp)
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scr |= SCR_HCE_BIT;
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scr |= SCR_HCE_BIT;
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reg_ctx = get_regs_ctx(ctx);
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write_ctx_reg(reg_ctx, CTX_SCR, scr);
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write_ctx_reg(reg_ctx, CTX_SCR, scr);
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write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
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write_ctx_reg(reg_ctx, CTX_LR, ep->pc);
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write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
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write_ctx_reg(reg_ctx, CTX_SPSR, ep->spsr);
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