From 5f902752e5c78112ebc8103b6d313171791ab755 Mon Sep 17 00:00:00 2001 From: Varun Wadekar Date: Wed, 5 Aug 2020 23:10:40 -0700 Subject: [PATCH 1/2] cpus: denver: skip DCO enable/disable for recent SKUs DCO is not supported by the SKUs released after MIDR_PN4. This patch skips enabling or disabling the DCO on these SKUs. Change-Id: Ic31a829de3ae560314d0fb5c5e867689d4ba243b Signed-off-by: Varun Wadekar --- lib/cpus/aarch64/denver.S | 18 ++++++++++++++---- 1 file changed, 14 insertions(+), 4 deletions(-) diff --git a/lib/cpus/aarch64/denver.S b/lib/cpus/aarch64/denver.S index 83427b84f..224ee2676 100644 --- a/lib/cpus/aarch64/denver.S +++ b/lib/cpus/aarch64/denver.S @@ -161,13 +161,19 @@ endfunc denver_disable_ext_debug * ---------------------------------------------------- */ func denver_enable_dco + /* DCO is not supported on PN5 and later */ + mrs x1, midr_el1 + mov_imm x2, DENVER_MIDR_PN4 + cmp x1, x2 + b.hi 1f + mov x18, x30 bl plat_my_core_pos mov x1, #1 lsl x1, x1, x0 msr s3_0_c15_c0_2, x1 mov x30, x18 - ret +1: ret endfunc denver_enable_dco /* ---------------------------------------------------- @@ -175,10 +181,14 @@ endfunc denver_enable_dco * ---------------------------------------------------- */ func denver_disable_dco - - mov x18, x30 + /* DCO is not supported on PN5 and later */ + mrs x1, midr_el1 + mov_imm x2, DENVER_MIDR_PN4 + cmp x1, x2 + b.hi 2f /* turn off background work */ + mov x18, x30 bl plat_my_core_pos mov x1, #1 lsl x1, x1, x0 @@ -194,7 +204,7 @@ func denver_disable_dco cbnz x2, 1b mov x30, x18 - ret +2: ret endfunc denver_disable_dco func check_errata_cve_2017_5715 From c23f5e1cb920bbf6d623a6f91719eb98a5292e52 Mon Sep 17 00:00:00 2001 From: anzhou Date: Wed, 5 Aug 2020 22:34:13 +0800 Subject: [PATCH 2/2] Tegra: common: disable GICC after domain off The the GIC CPU interface should be disabled after cpu off. The Tegra power management code should mark the connected core as asleep as part of the CPU off sequence. This patch disables the GICC after CPU off as a result. Signed-off-by: anzhou Change-Id: Ib1a3d8903f5e6d55bd2ee0c16134dbe2562235ea --- plat/nvidia/tegra/common/tegra_pm.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/plat/nvidia/tegra/common/tegra_pm.c b/plat/nvidia/tegra/common/tegra_pm.c index d0191d07d..27dd3a290 100644 --- a/plat/nvidia/tegra/common/tegra_pm.c +++ b/plat/nvidia/tegra/common/tegra_pm.c @@ -96,6 +96,9 @@ static int32_t tegra_pwr_domain_on(u_register_t mpidr) static void tegra_pwr_domain_off(const psci_power_state_t *target_state) { (void)tegra_soc_pwr_domain_off(target_state); + + /* disable GICC */ + tegra_gic_cpuif_deactivate(); } /*******************************************************************************