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Merge changes I94acd1bb,I0ece5226,I82d0a213,Ia4fc9456,Ic9fb7ed1 into integration 

* changes:
  rcar_gen3: plat: Update IPL and Secure Monitor Rev2.0.4
  rcar_gen3: drivers: rpc: Modify PFC code
  rcar_gen3: drivers: rpc: Change RPC PHY calibration setting
  rcar_gen3: drivers: ddr-b: Update DDR setting for H3, M3, M3N
  rcar_gen3: drivers: ddr-a: Update E3 DDR setting
This commit is contained in:
Sandrine Bailleux 2019-07-12 12:00:08 +00:00 committed by TrustedFirmware Code Review
parent 3ce3ce0738 363fb55a91
commit 9b35070249
18 changed files with 345 additions and 216 deletions
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6
drivers/renesas/rcar/auth/auth_mod.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights
* reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -25,7 +25,7 @@ extern int32_t rcar_get_certificate(const int32_t name, uint32_t *cert_addr);
#define RCAR_BOOT_KEY_CERT_NEW (0xE6300F00U)
#define RST_BASE (0xE6160000U)
#define RST_MODEMR (RST_BASE + 0x0060U)
#define MFISSOFTMDR (0xE6260600U)
#define MFISOFTMDR (0xE6260600U)
#define MODEMR_MD5_MASK (0x00000020U)
#define MODEMR_MD5_SHIFT (5U)
#define SOFTMD_BOOTMODE_MASK (0x00000001U)
@ -139,7 +139,7 @@ static int32_t normal_boot_verify(uint32_t a, uint32_t b, void *c)
void auth_mod_init(void)
{
#if RCAR_SECURE_BOOT
uint32_t soft_md = mmio_read_32(MFISSOFTMDR) & SOFTMD_BOOTMODE_MASK;
uint32_t soft_md = mmio_read_32(MFISOFTMDR) & SOFTMD_BOOTMODE_MASK;
uint32_t md = mmio_read_32(RST_MODEMR) & MODEMR_MD5_MASK;
uint32_t lcs, ret;

2
drivers/renesas/rcar/pfc/D3/pfc_init_d3.c
View File

@ -610,7 +610,7 @@ void pfc_init_d3(void)
/* initialize POC control register */
pfc_reg_write(PFC_POCCTRL0, 0xC00FFFFFU);
pfc_reg_write(PFC_POCCTRL1, 0XFFFFFFFEU);
pfc_reg_write(PFC_POCCTRL2, 0XFFFFFFFEU);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000U);
/* initialize LSI pin pull-up/down control */

16
drivers/renesas/rcar/pfc/E3/pfc_init_e3.c
View File

@ -122,7 +122,7 @@
#define GPSR5_SCK2_A BIT(7)
#define GPSR5_TX1 BIT(6)
#define GPSR5_RX1 BIT(5)
#define GPSR5_RTS0_TANS_A BIT(4)
#define GPSR5_RTS0_A BIT(4)
#define GPSR5_CTS0_A BIT(3)
#define GPSR5_TX0_A BIT(2)
#define GPSR5_RX0_A BIT(1)
@ -155,7 +155,7 @@
#define IPSR_4_FUNC(x) ((uint32_t)(x) << 4U)
#define IPSR_0_FUNC(x) ((uint32_t)(x) << 0U)
#define IOCTRL30_MASK (0x0007F000U)
#define POCCTRL0_MASK (0x0007F000U)
#define POC_SD3_DS_33V BIT(29)
#define POC_SD3_DAT7_33V BIT(28)
#define POC_SD3_DAT6_33V BIT(27)
@ -180,7 +180,7 @@
#define POC_SD0_CMD_33V BIT(1)
#define POC_SD0_CLK_33V BIT(0)
#define IOCTRL32_MASK (0xFFFFFFFEU)
#define POCCTRL2_MASK (0xFFFFFFFEU)
#define POC2_VREF_33V BIT(0)
#define MOD_SEL0_ADGB_A ((uint32_t)0U << 29U)
@ -561,7 +561,7 @@ void pfc_init_e3(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2_A
| GPSR5_RTS0_TANS_A
| GPSR5_RTS0_A
| GPSR5_CTS0_A);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_PWEN
| GPSR6_SSI_SDATA6
@ -581,7 +581,7 @@ void pfc_init_e3(void)
/* initialize POC control */
reg = mmio_read_32(PFC_POCCTRL0);
reg = ((reg & IOCTRL30_MASK) | POC_SD1_DAT3_33V
reg = ((reg & POCCTRL0_MASK) | POC_SD1_DAT3_33V
| POC_SD1_DAT2_33V
| POC_SD1_DAT1_33V
| POC_SD1_DAT0_33V
@ -594,9 +594,9 @@ void pfc_init_e3(void)
| POC_SD0_CMD_33V
| POC_SD0_CLK_33V);
pfc_reg_write(PFC_POCCTRL0, reg);
reg = mmio_read_32(PFC_POCCTRL1);
reg = (reg & IOCTRL32_MASK);
pfc_reg_write(PFC_POCCTRL1, reg);
reg = mmio_read_32(PFC_POCCTRL2);
reg = (reg & POCCTRL2_MASK);
pfc_reg_write(PFC_POCCTRL2, reg);
/* initialize LSI pin pull-up/down control */
pfc_reg_write(PFC_PUD0, 0xFDF80000U);

26
drivers/renesas/rcar/pfc/H3/pfc_init_h3_v1.c
View File

@ -119,11 +119,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@ -160,8 +160,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@ -323,8 +321,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@ -673,7 +671,6 @@ void pfc_init_h3_v1(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@ -829,11 +826,11 @@ void pfc_init_h3_v1(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@ -856,9 +853,7 @@ void pfc_init_h3_v1(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@ -996,8 +991,8 @@ void pfc_init_h3_v1(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@ -1153,6 +1148,7 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@ -1162,6 +1158,7 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@ -1182,4 +1179,5 @@ void pfc_init_h3_v1(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}

26
drivers/renesas/rcar/pfc/H3/pfc_init_h3_v2.c
View File

@ -121,11 +121,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@ -162,8 +162,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@ -325,8 +323,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@ -697,7 +695,6 @@ void pfc_init_h3_v2(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@ -862,11 +859,11 @@ void pfc_init_h3_v2(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@ -889,9 +886,7 @@ void pfc_init_h3_v2(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@ -1029,8 +1024,8 @@ void pfc_init_h3_v2(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@ -1186,6 +1181,7 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@ -1195,6 +1191,7 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@ -1215,4 +1212,5 @@ void pfc_init_h3_v2(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}

26
drivers/renesas/rcar/pfc/M3/pfc_init_m3.c
View File

@ -124,11 +124,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@ -165,8 +165,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@ -328,8 +326,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@ -792,7 +790,6 @@ void pfc_init_m3(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@ -957,11 +954,11 @@ void pfc_init_m3(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@ -984,9 +981,7 @@ void pfc_init_m3(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@ -1124,8 +1119,8 @@ void pfc_init_m3(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@ -1281,6 +1276,7 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@ -1290,6 +1286,7 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@ -1310,4 +1307,5 @@ void pfc_init_m3(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}

26
drivers/renesas/rcar/pfc/M3N/pfc_init_m3n.c
View File

@ -123,11 +123,11 @@
#define GPSR5_RX2_A BIT(11)
#define GPSR5_TX2_A BIT(10)
#define GPSR5_SCK2 BIT(9)
#define GPSR5_RTS1_TANS BIT(8)
#define GPSR5_RTS1 BIT(8)
#define GPSR5_CTS1 BIT(7)
#define GPSR5_TX1_A BIT(6)
#define GPSR5_RX1_A BIT(5)
#define GPSR5_RTS0_TANS BIT(4)
#define GPSR5_RTS0 BIT(4)
#define GPSR5_CTS0 BIT(3)
#define GPSR5_TX0 BIT(2)
#define GPSR5_RX0 BIT(1)
@ -164,8 +164,6 @@
#define GPSR6_SSI_SDATA0 BIT(2)
#define GPSR6_SSI_WS0129 BIT(1)
#define GPSR6_SSI_SCK0129 BIT(0)
#define GPSR7_HDMI1_CEC BIT(3)
#define GPSR7_HDMI0_CEC BIT(2)
#define GPSR7_AVS2 BIT(1)
#define GPSR7_AVS1 BIT(0)
@ -327,8 +325,8 @@
#define DRVCTRL11_D15(x) ((uint32_t)(x) << 24U)
#define DRVCTRL11_AVS1(x) ((uint32_t)(x) << 20U)
#define DRVCTRL11_AVS2(x) ((uint32_t)(x) << 16U)
#define DRVCTRL11_HDMI0_CEC(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_HDMI1_CEC(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_GP7_02(x) ((uint32_t)(x) << 12U)
#define DRVCTRL11_GP7_03(x) ((uint32_t)(x) << 8U)
#define DRVCTRL11_DU_DOTCLKIN0(x) ((uint32_t)(x) << 4U)
#define DRVCTRL11_DU_DOTCLKIN1(x) ((uint32_t)(x) << 0U)
#define DRVCTRL12_DU_DOTCLKIN2(x) ((uint32_t)(x) << 28U)
@ -699,7 +697,6 @@ void pfc_init_m3n(void)
| IPSR_24_FUNC(0)
| IPSR_20_FUNC(0)
| IPSR_16_FUNC(0)
| IPSR_12_FUNC(0)
| IPSR_8_FUNC(6)
| IPSR_4_FUNC(6)
| IPSR_0_FUNC(6));
@ -864,11 +861,11 @@ void pfc_init_m3n(void)
| GPSR5_RX2_A
| GPSR5_TX2_A
| GPSR5_SCK2
| GPSR5_RTS1_TANS
| GPSR5_RTS1
| GPSR5_CTS1
| GPSR5_TX1_A
| GPSR5_RX1_A
| GPSR5_RTS0_TANS
| GPSR5_RTS0
| GPSR5_SCK0);
pfc_reg_write(PFC_GPSR6, GPSR6_USB30_OVC
| GPSR6_USB30_PWEN
@ -891,9 +888,7 @@ void pfc_init_m3n(void)
| GPSR6_SSI_SDATA0
| GPSR6_SSI_WS0129
| GPSR6_SSI_SCK0129);
pfc_reg_write(PFC_GPSR7, GPSR7_HDMI1_CEC
| GPSR7_HDMI0_CEC
| GPSR7_AVS2
pfc_reg_write(PFC_GPSR7, GPSR7_AVS2
| GPSR7_AVS1);
/* initialize POC control register */
@ -1031,8 +1026,8 @@ void pfc_init_m3n(void)
| DRVCTRL11_D15(3)
| DRVCTRL11_AVS1(7)
| DRVCTRL11_AVS2(7)
| DRVCTRL11_HDMI0_CEC(7)
| DRVCTRL11_HDMI1_CEC(7)
| DRVCTRL11_GP7_02(7)
| DRVCTRL11_GP7_03(7)
| DRVCTRL11_DU_DOTCLKIN0(3)
| DRVCTRL11_DU_DOTCLKIN1(3));
pfc_reg_write(PFC_DRVCTRL11, reg);
@ -1188,6 +1183,7 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_POSNEG4, 0x00000000U);
mmio_write_32(GPIO_POSNEG5, 0x00000000U);
mmio_write_32(GPIO_POSNEG6, 0x00000000U);
mmio_write_32(GPIO_POSNEG7, 0x00000000U);
/* initialize general IO/interrupt switching */
mmio_write_32(GPIO_IOINTSEL0, 0x00000000U);
@ -1197,6 +1193,7 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_IOINTSEL4, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL5, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL6, 0x00000000U);
mmio_write_32(GPIO_IOINTSEL7, 0x00000000U);
/* initialize general output register */
mmio_write_32(GPIO_OUTDT1, 0x00000000U);
@ -1217,4 +1214,5 @@ void pfc_init_m3n(void)
mmio_write_32(GPIO_INOUTSEL5, 0x0000020EU);
#endif
mmio_write_32(GPIO_INOUTSEL6, 0x00013880U);
mmio_write_32(GPIO_INOUTSEL7, 0x00000000U);
}

2
drivers/renesas/rcar/pfc/V3M/pfc_init_v3m.c
View File

@ -709,7 +709,7 @@ void pfc_init_v3m(void)
| IOCTRL31_POC_VI0_DATA7
| IOCTRL31_POC_VI0_DATA6);
pfc_reg_write(PFC_POCCTRL1, 0x00000000);
pfc_reg_write(PFC_POCCTRL2, 0x00000000);
pfc_reg_write(PFC_TDSELCTRL0, 0x00000000);

2
drivers/renesas/rcar/pfc/pfc_regs.h
View File

@ -206,7 +206,7 @@
#define PFC_DRVCTRL24 (PFC_BASE + 0x0360U)
#define PFC_POCCTRL0 (PFC_BASE + 0x0380U)
#define PFC_IOCTRL31 (PFC_BASE + 0x0384U)
#define PFC_POCCTRL1 (PFC_BASE + 0x0388U)
#define PFC_POCCTRL2 (PFC_BASE + 0x0388U)
#define PFC_TDSELCTRL0 (PFC_BASE + 0x03C0U)
#define PFC_IOCTRL (PFC_BASE + 0x03E0U)
#define PFC_TSREG (PFC_BASE + 0x03E4U)

25
drivers/renesas/rcar/rpc/rpc_driver.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -11,11 +11,15 @@
#include <lib/mmio.h>
#include "cpg_registers.h"
#include "rpc_registers.h"
#include "rcar_def.h"
#include "rcar_private.h"
#include "rpc_registers.h"
#define MSTPSR9_RPC_BIT (0x00020000U)
#define RPC_CMNCR_MD_BIT (0x80000000U)
#define RPC_PHYCNT_CAL BIT(31)
#define RPC_PHYCNT_STRTIM_M3V1 (0x6 << 15UL)
#define RPC_PHYCNT_STRTIM (0x7 << 15UL)
static void rpc_enable(void)
{
@ -25,8 +29,25 @@ static void rpc_enable(void)
static void rpc_setup(void)
{
uint32_t product, cut, reg, phy_strtim;
if (mmio_read_32(RPC_CMNCR) & RPC_CMNCR_MD_BIT)
mmio_clrbits_32(RPC_CMNCR, RPC_CMNCR_MD_BIT);
product = mmio_read_32(RCAR_PRR) & RCAR_PRODUCT_MASK;
cut = mmio_read_32(RCAR_PRR) & RCAR_CUT_MASK;
if ((product == RCAR_PRODUCT_M3) && (cut < RCAR_CUT_VER30))
phy_strtim = RPC_PHYCNT_STRTIM_M3V1;
else
phy_strtim = RPC_PHYCNT_STRTIM;
reg = mmio_read_32(RPC_PHYCNT);
reg &= ~RPC_PHYCNT_STRTIM;
reg |= phy_strtim;
mmio_write_32(RPC_PHYCNT, reg);
reg |= RPC_PHYCNT_CAL;
mmio_write_32(RPC_PHYCNT, reg);
}
void rcar_rpc_init(void)

12
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -100,12 +100,8 @@ uint32_t init_ddr(void)
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02); /* 1GB */
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02); /* 4GB */
#else
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB */
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02); /* 2GB(default) */
#endif
#if RCAR_DRAM_DDR3L_MEMDUAL == 1
@ -894,10 +890,6 @@ uint32_t recovery_from_backup_mode(void)
#if RCAR_DRAM_DDR3L_MEMCONF == 0
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x0f030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 1
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#elif RCAR_DRAM_DDR3L_MEMCONF == 2
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030b02);
#else
WriteReg_32(DBSC_E3_DBMEMCONF00, 0x10030a02);
#endif

4
drivers/staging/renesas/rcar/ddr/ddr_a/ddr_init_e3.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -9,7 +9,7 @@
#include <stdint.h>
#define RCAR_E3_DDR_VERSION "rev.0.11"
#define RCAR_E3_DDR_VERSION "rev.0.12"
#ifdef ddr_qos_init_setting
#define REFRESH_RATE 3900 /* Average periodic refresh interval[ns]. Support 3900,7800 */

252
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -79,18 +79,18 @@ static uint32_t Prr_Cut;
char *pRCAR_DDR_VERSION;
uint32_t _cnf_BOARDTYPE;
static uint32_t *pDDR_REGDEF_TBL;
static const uint32_t *pDDR_REGDEF_TBL;
static uint32_t brd_clk;
static uint32_t brd_clkdiv;
static uint32_t brd_clkdiva;
static uint32_t ddr_mbps;
static uint32_t ddr_mbpsdiv;
static uint32_t ddr_tccd;
static struct _boardcnf *Boardcnf;
static uint32_t ddr_phyvalid;
static uint32_t ddr_phycaslice;
static volatile uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
static uint32_t ch_have_this_cs[CS_CNT];
static const struct _boardcnf *Boardcnf;
static uint32_t ddr_phyvalid;
static uint32_t ddr_density[DRAM_CH_CNT][CS_CNT];
static uint32_t ch_have_this_cs[CS_CNT] __attribute__ ((aligned(64)));
static uint32_t rdqdm_dly[DRAM_CH_CNT][CS_CNT][SLICE_CNT * 2][9];
static uint32_t max_density;
static uint32_t ddr0800_mul;
@ -228,7 +228,7 @@ static const uint32_t
/*******************************************************************************
* Prototypes
******************************************************************************/
static inline int32_t vch_nxt(int32_t pos);
static inline uint32_t vch_nxt(uint32_t pos);
static void cpg_write_32(uint32_t a, uint32_t v);
static void pll3_control(uint32_t high);
static inline void dsb_sev(void);
@ -328,9 +328,9 @@ static uint32_t wdqdm_ana1(uint32_t ch, uint32_t ddr_csn);
/*******************************************************************************
* macro for channel selection loop
******************************************************************************/
static inline int32_t vch_nxt(int32_t pos)
static inline uint32_t vch_nxt(uint32_t pos)
{
int32_t posn;
uint32_t posn;
for (posn = pos; posn < DRAM_CH_CNT; posn++) {
if (ddr_phyvalid & (1U << posn))
@ -364,26 +364,34 @@ static void pll3_control(uint32_t high)
uint32_t dataL, dataDIV, dataMUL, tmpDIV;
if (high) {
tmpDIV =
(1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
(ddr_mul * brd_clk * ddr_mbpsdiv + 1);
dataMUL =
(ddr_mul * (tmpDIV + 1) - 1) << 24;
tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
(brd_clk * ddr_mul) / 2;
dataMUL = (((ddr_mul * tmpDIV) - 1) << 24) |
(brd_clkdiva << 7);
Pll3Mode = 1;
loop_max = 2;
} else {
tmpDIV =
(1000 * ddr_mbpsdiv * brd_clkdiv * (brd_clkdiva + 1)) /
(ddr0800_mul * brd_clk * ddr_mbpsdiv + 1);
dataMUL =
(ddr0800_mul * (tmpDIV + 1) - 1) << 24;
tmpDIV = 3999 * brd_clkdiv * (brd_clkdiva + 1) /
(brd_clk * ddr0800_mul) / 2;
dataMUL = (((ddr0800_mul * tmpDIV) - 1) << 24) |
(brd_clkdiva << 7);
Pll3Mode = 0;
loop_max = 8;
}
if (tmpDIV) {
dataDIV = tmpDIV + 1;
} else {
switch (tmpDIV) {
case 1:
dataDIV = 0;
break;
case 2:
case 3:
case 4:
dataDIV = tmpDIV;
break;
default:
dataDIV = 6;
dataMUL = (dataMUL * tmpDIV) / 3;
break;
}
dataMUL = dataMUL | (brd_clkdiva << 7);
@ -478,8 +486,6 @@ static void pll3_control(uint32_t high)
} while ((dataL & CPG_PLLECR_PLL3ST_BIT) == 0);
dsb_sev();
}
return;
}
/*******************************************************************************
@ -891,17 +897,14 @@ struct _jedec_spec1 {
#define JS1_MR1(f) (0x04 | ((f)<<4))
#define JS1_MR2(f) (0x00 | ((f)<<3) | (f))
const struct _jedec_spec1 js1[JS1_FREQ_TBL_NUM] = {
/*A { 800, 6, 6, 4, 6 , 8, JS1_MR1(0), JS1_MR2(0) }, 533.333Mbps*/
/*A { 1600, 10, 12, 6, 10 , 8, JS1_MR1(1), JS1_MR2(1) }, 1066.666Mbps*/
/*A { 2400, 14, 16, 8, 16 , 8, JS1_MR1(2), JS1_MR2(2) }, 1600.000Mbps*/
/*B*/ {800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0) | 0x40}, /* 533.333Mbps */
/*B*/ {1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1) | 0x40}, /* 1066.666Mbps */
/*B*/ {2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2) | 0x40}, /* 1600.000Mbps */
/*A*/ {3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3)}, /* 2133.333Mbps */
/*A*/ {4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4)}, /* 2666.666Mbps */
/*A*/ {4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5)}, /* 3200.000Mbps */
/*A*/ {5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6)}, /* 3733.333Mbps */
/*A*/ {6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7)} /* 4266.666Mbps */
{ 800, 6, 6, 4, 6, 8, JS1_MR1(0), JS1_MR2(0)|0x40 }, /* 533.333Mbps */
{ 1600, 10, 12, 8, 10, 8, JS1_MR1(1), JS1_MR2(1)|0x40 }, /* 1066.666Mbps */
{ 2400, 14, 16, 12, 16, 8, JS1_MR1(2), JS1_MR2(2)|0x40 }, /* 1600.000Mbps */
{ 3200, 20, 22, 10, 20, 8, JS1_MR1(3), JS1_MR2(3) }, /* 2133.333Mbps */
{ 4000, 24, 28, 12, 24, 10, JS1_MR1(4), JS1_MR2(4) }, /* 2666.666Mbps */
{ 4800, 28, 32, 14, 30, 12, JS1_MR1(5), JS1_MR2(5) }, /* 3200.000Mbps */
{ 5600, 32, 36, 16, 34, 14, JS1_MR1(6), JS1_MR2(6) }, /* 3733.333Mbps */
{ 6400, 36, 40, 18, 40, 16, JS1_MR1(7), JS1_MR2(7) } /* 4266.666Mbps */
};
struct _jedec_spec2 {
@ -1225,7 +1228,7 @@ static void regif_pll_wa(void)
******************************************************************************/
static void ddrtbl_load(void)
{
int i;
uint32_t i;
uint32_t slice;
uint32_t csab;
uint32_t adr;
@ -1238,7 +1241,7 @@ static void ddrtbl_load(void)
***********************************************************************/
/* search jedec_spec1 index */
for (i = JS1_USABLEC_SPEC_LO; i < JS1_FREQ_TBL_NUM - 1; i++) {
if (js1[i].fx3 * 2 * ddr_mbpsdiv >= ddr_mbps * 3)
if (js1[i].fx3 * 2U * ddr_mbpsdiv >= ddr_mbps * 3U)
break;
}
if (JS1_USABLEC_SPEC_HI < i)
@ -1441,12 +1444,12 @@ static void ddrtbl_load(void)
#endif /* _def_LPDDR4_VREFCA */
if ((Prr_Product == PRR_PRODUCT_M3N)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7;
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 7000, 0) + 7U;
if (js2[JS2_tIEdly] > (RL))
js2[JS2_tIEdly] = RL;
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_11)) {
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4;
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 9000, 0) + 4U;
} else if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
js2[JS2_tIEdly] = _f_scale(ddr_mbps, ddr_mbpsdiv, 10000, 0);
@ -1528,7 +1531,8 @@ static void ddrtbl_load(void)
/***********************************************************************
FREQ_SEL_MULTICAST & PER_CS_TRAINING_MULTICAST SET (for safety)
***********************************************************************/
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x01);
/***********************************************************************
@ -1613,11 +1617,12 @@ static void ddrtbl_load(void)
******************************************************************************/
static void ddr_config_sub(void)
{
int32_t i;
uint32_t i;
uint32_t ch, slice;
uint32_t dataL;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
const uint32_t _par_CALVL_DEVICE_MAP = 1;
foreach_vch(ch) {
/***********************************************************************
BOARD SETTINGS (DQ,DM,VREF_DRIVING)
@ -1645,8 +1650,6 @@ static void ddr_config_sub(void)
/***********************************************************************
BOARD SETTINGS (CA,ADDR_SEL)
***********************************************************************/
const uint32_t _par_CALVL_DEVICE_MAP = 1;
dataL = (0x00ffffff & (uint32_t)(Boardcnf->ch[ch].ca_swap)) |
0x00888888;
@ -1771,11 +1774,20 @@ static void ddr_config_sub_h3v1x(void)
uint32_t dataL;
uint32_t tmp;
uint8_t high_byte[SLICE_CNT];
uint32_t ca_swizzle;
uint32_t ca;
uint32_t csmap;
uint32_t o_inv;
uint32_t inv;
uint32_t bit_soc;
uint32_t bit_mem;
uint32_t j;
const uint8_t o_mr15 = 0x55;
const uint8_t o_mr20 = 0x55;
const uint16_t o_mr32_mr40 = 0x5a3c;
foreach_vch(ch) {
uint32_t ca_swizzle;
uint32_t ca;
uint32_t csmap;
/***********************************************************************
BOARD SETTINGS (DQ,DM,VREF_DRIVING)
***********************************************************************/
@ -1817,15 +1829,6 @@ static void ddr_config_sub_h3v1x(void)
ddr_setval(ch, _reg_PHY_ADR_CALVL_DEVICE_MAP, 0x01);
for (slice = 0; slice < SLICE_CNT; slice++) {
const uint8_t o_mr15 = 0x55;
const uint8_t o_mr20 = 0x55;
const uint16_t o_mr32_mr40 = 0x5a3c;
uint32_t o_inv;
uint32_t inv;
uint32_t bit_soc;
uint32_t bit_mem;
uint32_t j;
ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_NUM,
0x01);
ddr_setval_s(ch, slice, _reg_PI_RDLVL_PATTERN_START,
@ -1862,6 +1865,14 @@ static void ddr_config(void)
uint32_t ch, slice;
uint32_t dataL;
uint32_t tmp;
int8_t _adj;
int16_t adj;
uint32_t dq;
union {
uint32_t ui32[4];
uint8_t ui8[16];
} patt;
uint16_t patm;
/***********************************************************************
configure ddrphy registers
@ -1876,11 +1887,6 @@ static void ddr_config(void)
WDQ_USER_PATT
***********************************************************************/
foreach_vch(ch) {
union {
uint32_t ui32[4];
uint8_t ui8[16];
} patt;
uint16_t patm;
for (slice = 0; slice < SLICE_CNT; slice++) {
patm = 0;
for (i = 0; i < 16; i++) {
@ -1905,48 +1911,65 @@ static void ddr_config(void)
CACS DLY
***********************************************************************/
dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
set_dfifrequency(0x1f);
} else {
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x01);
}
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN), 0x00U);
foreach_vch(ch) {
int16_t adj;
for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
for (i = 0; i < (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4); i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
reg_ddrphy_write(ch,
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
_cnf_DDR_PHY_ADR_V_REGSET[
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_V_REGSET_OFS]);
}
for (i = (_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM - 4);
i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
ddrtbl_setval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
reg_ddrphy_write(ch,
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]),
_cnf_DDR_PHY_ADR_G_REGSET[
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_G_REGSET_OFS]);
}
if (ddr_phycaslice == 1) {
for (i = 0; i < 6; i++) {
adj =
_f_scale_adj(Boardcnf->ch[ch].cacs_adj[i +
_reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
ddr_setval_s(ch, 2,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
adj = _f_scale_adj(
Boardcnf->ch[ch].cacs_adj[
i + _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM]);
ddrtbl_setval(_cnf_DDR_PHY_ADR_V_REGSET,
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
dataL + adj);
reg_ddrphy_write(ch,
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) +
0x0100,
_cnf_DDR_PHY_ADR_V_REGSET[
ddr_regdef_adr(
_reg_PHY_CLK_CACS_SLAVE_DELAY_X[i]) -
DDR_PHY_ADR_V_REGSET_OFS]);
}
}
}
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
set_dfifrequency(0x00);
} else {
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x01);
ddr_setval_ach(_reg_PHY_FREQ_SEL_INDEX, 0x00);
}
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
(0x01U << ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
/***********************************************************************
WDQDM DLY
***********************************************************************/
dataL = Boardcnf->dqdm_dly_w;
foreach_vch(ch) {
int8_t _adj;
int16_t adj;
uint32_t dq;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
@ -1967,9 +1990,6 @@ static void ddr_config(void)
***********************************************************************/
dataL = Boardcnf->dqdm_dly_r;
foreach_vch(ch) {
int8_t _adj;
int16_t adj;
uint32_t dq;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
dq = slice * 8 + i;
@ -2041,6 +2061,7 @@ static void dbsc_regset(void)
int32_t i;
uint32_t ch;
uint32_t dataL;
uint32_t dataL2;
uint32_t tmp[4];
/* RFC */
@ -2193,7 +2214,6 @@ static void dbsc_regset(void)
#define _par_DBRNK_VAL (0x7007)
for (i = 0; i < 4; i++) {
uint32_t dataL2;
dataL = (_par_DBRNK_VAL >> (i * 4)) & 0x0f;
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut > PRR_PRODUCT_11) && (i == 0)) {
@ -2559,7 +2579,7 @@ static uint32_t dfi_init_start(void)
retry = 0;
while (retry++ < RETRY_MAX) {
foreach_vch(ch) {
dataL = mmio_read_32(DBSC_INITCOMP(ch));
dataL = mmio_read_32(DBSC_DBDFISTAT(ch));
if (dataL & 0x00000001)
phytrainingok |= (1U << ch);
}
@ -2627,6 +2647,9 @@ static uint32_t set_term_code(void)
uint32_t chip_id[2];
uint32_t term_code;
uint32_t override;
uint32_t pvtr;
uint32_t pvtp;
uint32_t pvtn;
term_code = ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_DATA_TERM);
override = 0;
@ -2652,7 +2675,7 @@ static uint32_t set_term_code(void)
dataL =
ddrtbl_getval(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
dataL = (dataL & ~0x0001ffff) | term_code;
dataL = (dataL & 0xfffe0000) | term_code;
ddr_setval_ach(_reg_PHY_PAD_TERM_X[index], dataL);
}
} else if ((Prr_Product == PRR_PRODUCT_M3)
@ -2674,9 +2697,6 @@ static uint32_t set_term_code(void)
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
foreach_vch(ch) {
uint32_t pvtr;
uint32_t pvtp;
uint32_t pvtn;
dataL = ddr_getval(ch, _reg_PHY_PAD_TERM_X[0]);
pvtr = (dataL >> 12) & 0x1f;
pvtr += 8;
@ -2693,7 +2713,7 @@ static uint32_t set_term_code(void)
ddrtbl_getval
(_cnf_DDR_PHY_ADR_G_REGSET,
_reg_PHY_PAD_TERM_X[index]);
dataL = (dataL & ~0x0001ffff)
dataL = (dataL & 0xfffe0000)
| (pvtr << 12)
| (pvtn << 6)
| (pvtp);
@ -2969,6 +2989,7 @@ static uint32_t init_ddr(void)
uint32_t phytrainingok;
uint32_t ch, slice;
uint32_t err;
int16_t adj;
MSG_LF("init_ddr:0\n");
@ -3130,7 +3151,8 @@ static uint32_t init_ddr(void)
/***********************************************************************
exec pi_training
***********************************************************************/
ddr_setval_ach(_reg_PHY_FREQ_SEL_MULTICAST_EN, 0x00);
reg_ddrphy_write_a(ddr_regdef_adr(_reg_PHY_FREQ_SEL_MULTICAST_EN),
BIT(ddr_regdef_lsb(_reg_PHY_FREQ_SEL_MULTICAST_EN)));
ddr_setval_ach_as(_reg_PHY_PER_CS_TRAINING_MULTICAST_EN, 0x00);
if ((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut <= PRR_PRODUCT_11)) {
@ -3159,7 +3181,6 @@ static uint32_t init_ddr(void)
***********************************************************************/
dataL = Boardcnf->cacs_dly + _f_scale_adj(Boardcnf->cacs_dly_adj);
foreach_vch(ch) {
int16_t adj;
for (i = 0; i < _reg_PHY_CLK_CACS_SLAVE_DELAY_X_NUM; i++) {
adj = _f_scale_adj(Boardcnf->ch[ch].cacs_adj[i]);
ddr_setval(ch, _reg_PHY_CLK_CACS_SLAVE_DELAY_X[i],
@ -3563,6 +3584,7 @@ static uint32_t wdqdm_man(void)
{
uint32_t err, retry_cnt;
const uint32_t retry_max = 0x10;
uint32_t ch, ddr_csn, mr14_bkup[4][4];
ddr_setval_ach(_reg_PI_TDFI_WDQLVL_RW, (DBSC_DBTR(11) & 0xFF) + 12);
if (((Prr_Product == PRR_PRODUCT_H3) && (Prr_Cut > PRR_PRODUCT_11))
@ -3577,13 +3599,12 @@ static uint32_t wdqdm_man(void)
ddr_setval_ach(_reg_PI_TRFC_F1, (DBSC_DBTR(13) & 0x1FF));
retry_cnt = 0;
err = 0;
do {
if ((Prr_Product == PRR_PRODUCT_H3)
&& (Prr_Cut <= PRR_PRODUCT_11)) {
err = wdqdm_man1();
} else {
uint32_t ch, ddr_csn, mr14_bkup[4][4];
ddr_setval_ach(_reg_PI_WDQLVL_VREF_EN, 0x01);
ddr_setval_ach(_reg_PI_WDQLVL_VREF_NORMAL_STEPSIZE,
0x01);
@ -3720,15 +3741,15 @@ static uint32_t rdqdm_ana1(uint32_t ch, uint32_t ddr_csn)
int8_t _adj;
int16_t adj;
uint32_t dq;
int32_t min_win;
int32_t win;
uint32_t rdq_status_obs_select;
/***********************************************************************
analysis of training results
***********************************************************************/
err = 0;
for (slice = 0; slice < SLICE_CNT; slice++) {
int32_t min_win;
int32_t win;
uint32_t rdq_status_obs_select;
k = (Boardcnf->ch[ch].dqs_swap >> (4 * slice)) & 0x0f;
if (((k >= 2) && (ddr_csn < 2)) || ((k < 2) && (ddr_csn >= 2)))
continue;
@ -3828,6 +3849,7 @@ static uint32_t rdqdm_man1(void)
uint32_t ddr_csn;
#ifdef DDR_FAST_INIT
uint32_t slice;
uint32_t i, adj, dataL;
#endif/* DDR_FAST_INIT */
uint32_t err;
@ -3836,7 +3858,7 @@ static uint32_t rdqdm_man1(void)
***********************************************************************/
err = 0;
for (ddr_csn = 0; ddr_csn < CS_CNT; ddr_csn++) {
for (ddr_csn = 0; ddr_csn < CSAB_CNT; ddr_csn++) {
/* KICK RDQLVL */
err = swlvl1(ddr_csn, _reg_PI_RDLVL_CS, _reg_PI_RDLVL_REQ);
if (err)
@ -3870,8 +3892,6 @@ static uint32_t rdqdm_man1(void)
&& (Prr_Cut <= PRR_PRODUCT_11))
|| ((Prr_Product == PRR_PRODUCT_M3)
&& (Prr_Cut <= PRR_PRODUCT_10))) {
uint32_t i, adj, dataL;
for (slice = 0; slice < SLICE_CNT; slice++) {
for (i = 0; i <= 8; i++) {
if (i == 8)
@ -3948,7 +3968,7 @@ static int32_t _find_change(uint64_t val, uint32_t dir)
int32_t i;
uint32_t startval;
uint32_t curval;
const uint32_t VAL_END = 0x3f;
const int32_t VAL_END = 0x3f;
if (dir == 0) {
startval = (val & 0x01);
@ -4004,6 +4024,8 @@ static uint32_t rx_offset_cal(void)
uint32_t tmp;
uint32_t tmp_ach_as[DRAM_CH_CNT][SLICE_CNT];
uint64_t val[DRAM_CH_CNT][SLICE_CNT][_reg_PHY_RX_CAL_X_NUM];
uint64_t tmpval;
int32_t lsb, msb;
ddr_setval_ach_as(_reg_PHY_RX_CAL_OVERRIDE, 0x01);
foreach_vch(ch) {
@ -4041,8 +4063,6 @@ static uint32_t rx_offset_cal(void)
foreach_vch(ch) {
for (slice = 0; slice < SLICE_CNT; slice++) {
for (index = 0; index < _reg_PHY_RX_CAL_X_NUM; index++) {
uint64_t tmpval;
int32_t lsb, msb;
tmpval = val[ch][slice][index];
lsb = _find_change(tmpval, 0);
msb =
@ -4230,15 +4250,15 @@ int32_t rcar_dram_init(void)
if (Prr_Product == PRR_PRODUCT_H3) {
if (Prr_Cut <= PRR_PRODUCT_11) {
pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[0][0];
pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[0][0];
} else {
pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[2][0];
pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[2][0];
}
} else if (Prr_Product == PRR_PRODUCT_M3) {
pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[1][0];
pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[1][0];
} else if ((Prr_Product == PRR_PRODUCT_M3N)
|| (Prr_Product == PRR_PRODUCT_V3H)) {
pDDR_REGDEF_TBL = (uint32_t *) & DDR_REGDEF_TBL[3][0];
pDDR_REGDEF_TBL = (const uint32_t *)&DDR_REGDEF_TBL[3][0];
} else {
FATAL_MSG("BL2: DDR:Unknown Product\n");
return 0xff;
@ -4259,7 +4279,7 @@ int32_t rcar_dram_init(void)
FATAL_MSG("BL2: DDR:Unknown Board\n");
return 0xff;
}
Boardcnf = (struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
Boardcnf = (const struct _boardcnf *)&boardcnfs[_cnf_BOARDTYPE];
/* RCAR_DRAM_SPLIT_2CH (2U) */
#if RCAR_DRAM_SPLIT == 2
@ -4327,6 +4347,8 @@ int32_t rcar_dram_init(void)
Adjust tccd
***********************************************************************/
dataL = (0x00006000 & mmio_read_32(RST_MODEMR)) >> 13;
bus_mbps = 0;
bus_mbpsdiv = 0;
switch (dataL) {
case 0:
bus_mbps = brd_clk * 0x60 * 2;

116
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_config.c
View File

@ -1,10 +1,10 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#define BOARDNUM 20
#define BOARDNUM 22
#define BOARD_JUDGE_AUTO
#ifdef BOARD_JUDGE_AUTO
@ -1425,6 +1425,108 @@ static const struct _boardcnf boardcnfs[BOARDNUM] = {
}
}
},
/* boardcnf[20] RENESAS KRIEK 16Gbit/2rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0x04},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0x04},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
},
/* boardcnf[21] RENESAS KRIEK 16Gbit/1rank/2ch board with M3-W/SoC */
{
0x03,
0x01,
0x02c0,
0,
0x0300,
0x00a0,
{
{
{0x04, 0xff},
0x00345201,
0x3201,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
},
{
{0x04, 0xff},
0x00302154,
0x2310,
{0x01672543, 0x45361207, 0x45632107, 0x60715234},
{0x08, 0x08, 0x08, 0x08},
WDQLVL_PAT,
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0},
{0, 0, 0, 0},
{0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0,
0, 0, 0, 0, 0, 0, 0, 0}
}
}
}
};
void boardcnf_get_brd_clk(uint32_t brd, uint32_t * clk, uint32_t * div)
@ -1522,10 +1624,10 @@ static const uint32_t TermcodeBySample[20][3] = {
#define GPIO_INDT5 0xE605500CU
#define GPIO_INDT6 0xE605540CU
#define BIT25 (1<<25)
#define BIT22 (1<<22)
#define BIT15 (1<<15)
#define BIT0 (1)
#define BIT25 BIT(25)
#define BIT22 BIT(22)
#define BIT15 BIT(15)
#define BIT0 BIT(0)
#define GPIO_GPSR6 (0xE6060118U)
#if (RCAR_GEN3_ULCB == 0)
@ -1673,7 +1775,7 @@ static uint32_t _board_judge(void)
/* RENESAS SALVATOR-X (M3-W/SIP) */
brd = 0;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut < PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W Ver.1.3/SIP) */
/* RENESAS SALVATOR-X (M3-W Ver.1.x/SIP) */
brd = 19;
} else if ((Prr_Product == PRR_PRODUCT_M3) && (Prr_Cut >= PRR_PRODUCT_30)) {
/* RENESAS SALVATOR-X (M3-W ver.3.0/SIP) */

12
drivers/staging/renesas/rcar/ddr/ddr_b/boot_init_dram_regdef.h
View File

@ -4,7 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#define RCAR_DDR_VERSION "rev.0.35"
#define RCAR_DDR_VERSION "rev.0.36"
#define DRAM_CH_CNT (0x04)
#define SLICE_CNT (0x04)
#define CS_CNT (0x02)
@ -144,11 +144,11 @@
#define DBSC_DBDFIPMSTRCNF 0xE6790520U
#define DBSC_DBDFICUPDCNF 0xE679052CU
#define DBSC_INITCOMP(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_INITCOMP_0 0xE6790600U
#define DBSC_INITCOMP_1 0xE6790640U
#define DBSC_INITCOMP_2 0xE6790680U
#define DBSC_INITCOMP_3 0xE67906C0U
#define DBSC_DBDFISTAT(ch) (0xE6790600U + 0x40U * (ch))
#define DBSC_DBDFISTAT_0 0xE6790600U
#define DBSC_DBDFISTAT_1 0xE6790640U
#define DBSC_DBDFISTAT_2 0xE6790680U
#define DBSC_DBDFISTAT_3 0xE67906C0U
#define DBSC_DBDFICNT(ch) (0xE6790604U + 0x40U * (ch))
#define DBSC_DBDFICNT_0 0xE6790604U

4
drivers/staging/renesas/rcar/ddr/ddr_b/ddr_regdef.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -1182,7 +1182,7 @@
#define DDR_REGDEF_LEN(regdef) (((regdef)>>16)&0xff)
#define DDR_REGDEF_LSB(regdef) (((regdef)>>24)&0xff)
const static uint32_t DDR_REGDEF_TBL[4][1173] = {
static const uint32_t DDR_REGDEF_TBL[4][1173] = {
{
/*0000*/ 0xffffffffU,
/*0001*/ 0xffffffffU,

2
drivers/staging/renesas/rcar/ddr/ddr_b/init_dram_tbl_h3.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2018, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/

2
plat/renesas/rcar/include/rcar_version.h
View File

@ -9,7 +9,7 @@
#include <arch_helpers.h>
#define VERSION_OF_RENESAS "2.0.3"
#define VERSION_OF_RENESAS "2.0.4"
#define VERSION_OF_RENESAS_MAXLEN (128)
extern const uint8_t version_of_renesas[VERSION_OF_RENESAS_MAXLEN];