feat(morello): configure DMC-Bing mode
Based on the SCC configuration value obtained from the SDS platform information structure configure DMC-Bing Server or Client mode after zeroing out the memory. Signed-off-by: Chandni Cherukuri <chandni.cherukuri@arm.com> Change-Id: I0555fa06c9c1906264848f4e32ca413b4742cdee
This commit is contained in:
Chandni Cherukuri
parent
2d39b39704
commit
9b8c431e2b
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@ -23,12 +23,14 @@
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* - Remote DDR size in bytes, DDR memory in slave board
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* - slave_count
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* - multichip mode
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* - scc configuration
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*/
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struct morello_plat_info {
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uint64_t local_ddr_size;
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uint64_t remote_ddr_size;
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uint8_t slave_count;
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bool multichip_mode;
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uint32_t scc_config;
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} __packed;
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/* Compile time assertion to ensure the size of structure is 18 bytes */
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@ -79,6 +81,8 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info)
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{
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uint64_t dram2_size;
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uint32_t val;
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uint64_t tag_mem_base;
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uint64_t usable_mem_size;
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INFO("Total DIMM size: %uGB\n",
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(uint32_t)(plat_info->local_ddr_size / 0x40000000));
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@ -115,6 +119,63 @@ static void dmc_ecc_setup(struct morello_plat_info *plat_info)
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continue;
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}
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/* Configure Bing client/server mode based on SCC configuration */
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if (plat_info->scc_config & MORELLO_SCC_CLIENT_MODE_MASK) {
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INFO("Configuring DMC Bing in client mode\n");
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usable_mem_size = plat_info->local_ddr_size -
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(plat_info->local_ddr_size / 128ULL);
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/* Linear DDR address */
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tag_mem_base = usable_mem_size;
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tag_mem_base = tag_mem_base / 4;
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/* Reverse translation */
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if (tag_mem_base < ARM_DRAM1_BASE) {
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tag_mem_base += ARM_DRAM1_BASE;
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} else {
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tag_mem_base = tag_mem_base - ARM_DRAM1_BASE +
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ARM_DRAM2_BASE;
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}
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mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x1);
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mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x1);
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mmio_write_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x1);
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mmio_write_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x1);
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if (plat_info->scc_config & MORELLO_SCC_C1_TAG_CACHE_EN_MASK) {
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mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x2);
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mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x2);
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INFO("C1 Tag Cache Enabled\n");
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}
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if (plat_info->scc_config & MORELLO_SCC_C2_TAG_CACHE_EN_MASK) {
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mmio_setbits_32(MORELLO_DMC0_TAG_CACHE_CFG, 0x4);
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mmio_setbits_32(MORELLO_DMC1_TAG_CACHE_CFG, 0x4);
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INFO("C2 Tag Cache Enabled\n");
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}
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mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL,
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(uint32_t)tag_mem_base);
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mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL,
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(uint32_t)tag_mem_base);
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mmio_write_32(MORELLO_DMC0_MEM_ADDR_CTL2,
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(uint32_t)(tag_mem_base >> 32));
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mmio_write_32(MORELLO_DMC1_MEM_ADDR_CTL2,
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(uint32_t)(tag_mem_base >> 32));
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mmio_setbits_32(MORELLO_DMC0_MEM_ACCESS_CTL,
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MORELLO_DMC_MEM_ACCESS_DIS);
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mmio_setbits_32(MORELLO_DMC1_MEM_ACCESS_CTL,
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MORELLO_DMC_MEM_ACCESS_DIS);
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INFO("Tag base set to 0x%lx\n", tag_mem_base);
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plat_info->local_ddr_size = usable_mem_size;
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} else {
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INFO("Configuring DMC Bing in server mode\n");
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mmio_write_32(MORELLO_DMC0_CAP_CTRL_REG, 0x0);
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mmio_write_32(MORELLO_DMC1_CAP_CTRL_REG, 0x0);
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}
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INFO("Enabling ECC on DMCs\n");
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/* Enable ECC in DMCs */
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mmio_setbits_32(MORELLO_DMC0_ERR0CTLR0_REG,
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@ -18,7 +18,7 @@
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/* SDS Platform information defines */
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#define MORELLO_SDS_PLATFORM_INFO_STRUCT_ID U(8)
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#define MORELLO_SDS_PLATFORM_INFO_OFFSET U(0)
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#define MORELLO_SDS_PLATFORM_INFO_SIZE U(18)
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#define MORELLO_SDS_PLATFORM_INFO_SIZE U(22)
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#define MORELLO_MAX_DDR_CAPACITY U(0x1000000000)
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#define MORELLO_MAX_SLAVE_COUNT U(16)
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@ -27,29 +27,64 @@
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#define MORELLO_SDS_BL33_INFO_OFFSET U(0)
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#define MORELLO_SDS_BL33_INFO_SIZE U(12)
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#define MORELLO_SCC_SERVER_MODE U(0)
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#define MORELLO_SCC_CLIENT_MODE_MASK U(1)
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#define MORELLO_SCC_C1_TAG_CACHE_EN_MASK U(4)
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#define MORELLO_SCC_C2_TAG_CACHE_EN_MASK U(8)
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/* Base address of non-secure SRAM where Platform information will be filled */
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#define MORELLO_PLATFORM_INFO_BASE UL(0x06000000)
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/* DMC memory status registers */
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#define MORELLO_DMC0_MEMC_STATUS_REG 0x4E000000
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#define MORELLO_DMC1_MEMC_STATUS_REG 0x4E100000
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#define MORELLO_DMC0_MEMC_STATUS_REG UL(0x4E000000)
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#define MORELLO_DMC1_MEMC_STATUS_REG UL(0x4E100000)
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#define MORELLO_DMC_MEMC_STATUS_MASK U(7)
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/* DMC memory command registers */
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#define MORELLO_DMC0_MEMC_CMD_REG 0x4E000008
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#define MORELLO_DMC1_MEMC_CMD_REG 0x4E100008
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#define MORELLO_DMC0_MEMC_CMD_REG UL(0x4E000008)
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#define MORELLO_DMC1_MEMC_CMD_REG UL(0x4E100008)
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/* DMC capability control register */
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#define MORELLO_DMC0_CAP_CTRL_REG UL(0x4E000D00)
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#define MORELLO_DMC1_CAP_CTRL_REG UL(0x4E100D00)
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/* DMC tag cache control register */
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#define MORELLO_DMC0_TAG_CACHE_CTL UL(0x4E000D04)
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#define MORELLO_DMC1_TAG_CACHE_CTL UL(0x4E100D04)
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/* DMC tag cache config register */
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#define MORELLO_DMC0_TAG_CACHE_CFG UL(0x4E000D08)
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#define MORELLO_DMC1_TAG_CACHE_CFG UL(0x4E100D08)
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/* DMC memory access control register */
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#define MORELLO_DMC0_MEM_ACCESS_CTL UL(0x4E000D0C)
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#define MORELLO_DMC1_MEM_ACCESS_CTL UL(0x4E100D0C)
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#define MORELLO_DMC_MEM_ACCESS_DIS (1UL << 16)
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/* DMC memory address control register */
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#define MORELLO_DMC0_MEM_ADDR_CTL UL(0x4E000D10)
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#define MORELLO_DMC1_MEM_ADDR_CTL UL(0x4E100D10)
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/* DMC memory address control 2 register */
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#define MORELLO_DMC0_MEM_ADDR_CTL2 UL(0x4E000D14)
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#define MORELLO_DMC1_MEM_ADDR_CTL2 UL(0x4E100D14)
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/* DMC special control register */
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#define MORELLO_DMC0_SPL_CTL_REG UL(0x4E000D18)
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#define MORELLO_DMC1_SPL_CTL_REG UL(0x4E100D18)
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/* DMC ERR0CTLR0 registers */
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#define MORELLO_DMC0_ERR0CTLR0_REG 0x4E000708
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#define MORELLO_DMC1_ERR0CTLR0_REG 0x4E100708
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#define MORELLO_DMC0_ERR0CTLR0_REG UL(0x4E000708)
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#define MORELLO_DMC1_ERR0CTLR0_REG UL(0x4E100708)
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/* DMC ECC in ERR0CTLR0 register */
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#define MORELLO_DMC_ERR0CTLR0_ECC_EN U(9)
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/* DMC ERR2STATUS register */
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#define MORELLO_DMC0_ERR2STATUS_REG 0x4E000790
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#define MORELLO_DMC1_ERR2STATUS_REG 0x4E100790
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#define MORELLO_DMC0_ERR2STATUS_REG UL(0x4E000790)
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#define MORELLO_DMC1_ERR2STATUS_REG UL(0x4E100790)
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/* DMC memory commands */
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#define MORELLO_DMC_MEMC_CMD_CONFIG U(0)
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