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Revert workaround for A77 erratum 1800714 

This errata workaround did not work as intended and was revised in
subsequent SDEN releases so we are reverting this change.

This is the patch being reverted:
https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/4686

Signed-off-by: John Powell <john.powell@arm.com>
Change-Id: I8554c75d7217331c7effd781b5f7f49b781bbebe
This commit is contained in:
johpow01 2020-11-12 14:15:41 -06:00
parent 95ed9a9e0d
commit 9bbc03a6e0
4 changed files with 0 additions and 47 deletions
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3
docs/design/cpu-specific-build-macros.rst
View File

@ -254,9 +254,6 @@ For Cortex-A77, the following errata build flags are defined :
- ``ERRATA_A77_1508412``: This applies errata 1508412 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p0 of the CPU.
- ``ERRATA_A77_1800714``: This applies errata 1800714 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.
- ``ERRATA_A77_1925769``: This applies errata 1925769 workaround to Cortex-A77
CPU. This needs to be enabled only for revision <= r1p1 of the CPU.

1
include/lib/cpus/aarch64/cortex_a77.h
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@ -17,7 +17,6 @@
******************************************************************************/
#define CORTEX_A77_CPUECTLR_EL1 S3_0_C15_C1_4
#define CORTEX_A77_CPUECTLR_EL1_BIT_8 (ULL(1) << 8)
#define CORTEX_A77_CPUECTLR_EL1_BIT_53 (ULL(1) << 53)
/*******************************************************************************
* CPU Power Control register specific definitions.

35
lib/cpus/aarch64/cortex_a77.S
View File

@ -85,35 +85,6 @@ func check_errata_1508412_0
b cpu_rev_var_ls
endfunc check_errata_1508412_0
/* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1800714.
* This applies to revision <= r1p1 of Cortex A77.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a77_1800714_wa
/* Compare x0 against revision <= r1p1 */
mov x17, x30
bl check_errata_1800714
cbz x0, 1f
/* Disable allocation of splintered pages in the L2 TLB */
mrs x1, CORTEX_A77_CPUECTLR_EL1
orr x1, x1, CORTEX_A77_CPUECTLR_EL1_BIT_53
msr CORTEX_A77_CPUECTLR_EL1, x1
isb
1:
ret x17
endfunc errata_a77_1800714_wa
func check_errata_1800714
/* Applies to everything <= r1p1 */
mov x1, #0x11
b cpu_rev_var_ls
endfunc check_errata_1800714
/* --------------------------------------------------
* Errata Workaround for Cortex A77 Errata #1925769.
* This applies to revision <= r1p1 of Cortex A77.
@ -158,11 +129,6 @@ func cortex_a77_reset_func
bl errata_a77_1508412_wa
#endif
#if ERRATA_A77_1800714
mov x0, x18
bl errata_a77_1800714_wa
#endif
#if ERRATA_A77_1925769
mov x0, x18
bl errata_a77_1925769_wa
@ -202,7 +168,6 @@ func cortex_a77_errata_report
* checking functions of each errata.
*/
report_errata ERRATA_A77_1508412, cortex_a77, 1508412
report_errata ERRATA_A77_1800714, cortex_a77, 1800714
report_errata ERRATA_A77_1925769, cortex_a77, 1925769
ldp x8, x30, [sp], #16

8
lib/cpus/cpu-ops.mk
View File

@ -282,10 +282,6 @@ ERRATA_A76_1868343 ?=0
# only to revision <= r1p0 of the Cortex A77 cpu.
ERRATA_A77_1508412 ?=0
# Flag to apply erratum 1800714 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1800714 ?=0
# Flag to apply erratum 1925769 workaround during reset. This erratum applies
# only to revision <= r1p1 of the Cortex A77 cpu.
ERRATA_A77_1925769 ?=0
@ -563,10 +559,6 @@ $(eval $(call add_define,ERRATA_A76_1868343))
$(eval $(call assert_boolean,ERRATA_A77_1508412))
$(eval $(call add_define,ERRATA_A77_1508412))
# Process ERRATA_A77_1800714 flag
$(eval $(call assert_boolean,ERRATA_A77_1800714))
$(eval $(call add_define,ERRATA_A77_1800714))
# Process ERRATA_A77_1925769 flag
$(eval $(call assert_boolean,ERRATA_A77_1925769))
$(eval $(call add_define,ERRATA_A77_1925769))