rockchip: move pmu registers into another header for rk3399
This moves the PMU register definitions into another file for use in later patches. Change-Id: I8b5f1e7938b63ada6a743cf9661c3e474e96e4e4 Signed-off-by: Derek Basehore <dbasehore@chromium.org> Signed-off-by: Caesar Wang <wxt@rock-chips.com>
This commit is contained in:
Caesar Wang
parent
ad09652c41
commit
9c68748eaf
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@ -31,6 +31,8 @@
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#ifndef __PMU_H__
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#define __PMU_H__
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#include <pmu_regs.h>
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/* Allocate sp reginon in pmusram */
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#define PSRAM_SP_SIZE 0x80
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#define PSRAM_SP_BOTTOM (PSRAM_SP_TOP - PSRAM_SP_SIZE)
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@ -751,72 +753,7 @@ enum pmu_core_pwr_st {
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STANDBY_BY_WFIL2_CLUSTER_B,
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};
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#define PMU_WKUP_CFG0 0x00
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#define PMU_WKUP_CFG1 0x04
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#define PMU_WKUP_CFG2 0x08
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#define PMU_WKUP_CFG3 0x0c
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#define PMU_WKUP_CFG4 0x10
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#define PMU_PWRDN_CON 0x14
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#define PMU_PWRDN_ST 0x18
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#define PMU_PLL_CON 0x1c
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#define PMU_PWRMODE_CON 0x20
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#define PMU_SFT_CON 0x24
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#define PMU_INT_CON 0x28
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#define PMU_INT_ST 0x2c
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#define PMU_GPIO0_POS_INT_CON 0x30
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#define PMU_GPIO0_NEG_INT_CON 0x34
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#define PMU_GPIO1_POS_INT_CON 0x38
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#define PMU_GPIO1_NEG_INT_CON 0x3c
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#define PMU_GPIO0_POS_INT_ST 0x40
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#define PMU_GPIO0_NEG_INT_ST 0x44
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#define PMU_GPIO1_POS_INT_ST 0x48
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#define PMU_GPIO1_NEG_INT_ST 0x4c
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#define PMU_PWRDN_INTEN 0x50
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#define PMU_PWRDN_STATUS 0x54
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#define PMU_WAKEUP_STATUS 0x58
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#define PMU_BUS_CLR 0x5c
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#define PMU_BUS_IDLE_REQ 0x60
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#define PMU_BUS_IDLE_ST 0x64
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#define PMU_BUS_IDLE_ACK 0x68
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#define PMU_CCI500_CON 0x6c
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#define PMU_ADB400_CON 0x70
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#define PMU_ADB400_ST 0x74
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#define PMU_POWER_ST 0x78
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#define PMU_CORE_PWR_ST 0x7c
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#define PMU_OSC_CNT 0x80
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#define PMU_PLLLOCK_CNT 0x84
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#define PMU_PLLRST_CNT 0x88
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#define PMU_STABLE_CNT 0x8c
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#define PMU_DDRIO_PWRON_CNT 0x90
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#define PMU_WAKEUP_RST_CLR_CNT 0x94
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#define PMU_DDR_SREF_ST 0x98
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#define PMU_SCU_L_PWRDN_CNT 0x9c
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#define PMU_SCU_L_PWRUP_CNT 0xa0
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#define PMU_SCU_B_PWRDN_CNT 0xa4
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#define PMU_SCU_B_PWRUP_CNT 0xa8
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#define PMU_GPU_PWRDN_CNT 0xac
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#define PMU_GPU_PWRUP_CNT 0xb0
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#define PMU_CENTER_PWRDN_CNT 0xb4
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#define PMU_CENTER_PWRUP_CNT 0xb8
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#define PMU_TIMEOUT_CNT 0xbc
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#define PMU_CPU0APM_CON 0xc0
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#define PMU_CPU1APM_CON 0xc4
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#define PMU_CPU2APM_CON 0xc8
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#define PMU_CPU3APM_CON 0xcc
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#define PMU_CPU0BPM_CON 0xd0
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#define PMU_CPU1BPM_CON 0xd4
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#define PMU_NOC_AUTO_ENA 0xd8
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#define PMU_PWRDN_CON1 0xdc
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#define PMUGRF_GPIO0A_IOMUX 0x00
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#define PMUGRF_GPIO1A_IOMUX 0x10
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#define PMUGRF_GPIO1C_IOMUX 0x18
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#define PMUGRF_GPIO0A6_IOMUX_SHIFT 12
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#define PMUGRF_GPIO0A6_IOMUX_PWM 0x1
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#define PMUGRF_GPIO1C3_IOMUX_SHIFT 6
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#define PMUGRF_GPIO1C3_IOMUX_PWM 0x1
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/* Specific features required */
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#define AP_PWROFF 0x0a
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#define GPIO0A0_SMT_ENABLE BITS_WITH_WMASK(1, 3, 0)
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@ -824,51 +761,6 @@ enum pmu_core_pwr_st {
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#define TSADC_INT_PIN 38
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#define CORES_PM_DISABLE 0x0
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#define CPU_AXI_QOS_ID_COREID 0x00
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#define CPU_AXI_QOS_REVISIONID 0x04
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#define CPU_AXI_QOS_PRIORITY 0x08
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#define CPU_AXI_QOS_MODE 0x0c
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#define CPU_AXI_QOS_BANDWIDTH 0x10
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#define CPU_AXI_QOS_SATURATION 0x14
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#define CPU_AXI_QOS_EXTCONTROL 0x18
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#define CPU_AXI_QOS_NUM_REGS 0x07
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#define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000
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#define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000
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#define CPU_AXI_DMAC0_QOS_BASE 0xffa64200
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#define CPU_AXI_DMAC1_QOS_BASE 0xffa64280
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#define CPU_AXI_DCF_QOS_BASE 0xffa64180
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#define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100
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#define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080
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#define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000
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#define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300
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#define CPU_AXI_GIC_QOS_BASE 0xffa78000
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#define CPU_AXI_SDIO_QOS_BASE 0xffa76000
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#define CPU_AXI_SDMMC_QOS_BASE 0xffa74000
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#define CPU_AXI_EMMC_QOS_BASE 0xffa58000
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#define CPU_AXI_GMAC_QOS_BASE 0xffa5c000
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#define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000
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#define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080
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#define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100
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#define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180
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#define CPU_AXI_GPU_QOS_BASE 0xffae0000
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#define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000
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#define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000
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#define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080
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#define CPU_AXI_RGA_R_QOS_BASE 0xffab0000
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#define CPU_AXI_RGA_W_QOS_BASE 0xffab0080
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#define CPU_AXI_IEP_QOS_BASE 0xffa98000
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#define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000
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#define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080
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#define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000
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#define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000
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#define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080
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#define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000
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#define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080
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#define CPU_AXI_HDCP_QOS_BASE 0xffa90000
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#define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080
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#define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180
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#define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100
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#define PD_CTR_LOOP 500
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#define CHK_CPU_LOOP 500
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@ -876,32 +768,6 @@ enum pmu_core_pwr_st {
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#define GRF_SOC_CON4 0x0e210
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#define GRF_GPIO2A_IOMUX 0xe000
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#define GRF_GPIO2B_IOMUX 0xe004
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#define GRF_GPIO2C_IOMUX 0xe008
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#define GRF_GPIO2D_IOMUX 0xe00c
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#define GRF_GPIO3A_IOMUX 0xe010
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#define GRF_GPIO3B_IOMUX 0xe014
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#define GRF_GPIO3C_IOMUX 0xe018
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#define GRF_GPIO3D_IOMUX 0xe01c
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#define GRF_GPIO4A_IOMUX 0xe020
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#define GRF_GPIO4B_IOMUX 0xe024
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#define GRF_GPIO4C_IOMUX 0xe028
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#define GRF_GPIO4D_IOMUX 0xe02c
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#define GRF_GPIO2A_P 0xe040
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#define GRF_GPIO2B_P 0xe044
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#define GRF_GPIO2C_P 0xe048
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#define GRF_GPIO2D_P 0xe04C
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#define GRF_GPIO3A_P 0xe050
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#define GRF_GPIO3B_P 0xe054
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#define GRF_GPIO3C_P 0xe058
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#define GRF_GPIO3D_P 0xe05C
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#define GRF_GPIO4A_P 0xe060
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#define GRF_GPIO4B_P 0xe064
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#define GRF_GPIO4C_P 0xe068
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#define GRF_GPIO4D_P 0xe06C
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#define PMUGRF_GPIO0A_SMT 0x0120
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#define PMUGRF_SOC_CON0 0x0180
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@ -0,0 +1,172 @@
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/*
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* Copyright (c) 2016, ARM Limited and Contributors. All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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*
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* Redistributions of source code must retain the above copyright notice, this
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* list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright notice,
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* this list of conditions and the following disclaimer in the documentation
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* and/or other materials provided with the distribution.
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*
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* Neither the name of ARM nor the names of its contributors may be used
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* to endorse or promote products derived from this software without specific
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* prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
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* LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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* CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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* SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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* INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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* CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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* ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef __PMU_REGS_H__
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#define __PMU_REGS_H__
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#define PMU_WKUP_CFG0 0x00
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#define PMU_WKUP_CFG1 0x04
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#define PMU_WKUP_CFG2 0x08
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#define PMU_WKUP_CFG3 0x0c
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#define PMU_WKUP_CFG4 0x10
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#define PMU_PWRDN_CON 0x14
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#define PMU_PWRDN_ST 0x18
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#define PMU_PLL_CON 0x1c
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#define PMU_PWRMODE_CON 0x20
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#define PMU_SFT_CON 0x24
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#define PMU_INT_CON 0x28
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#define PMU_INT_ST 0x2c
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#define PMU_GPIO0_POS_INT_CON 0x30
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#define PMU_GPIO0_NEG_INT_CON 0x34
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#define PMU_GPIO1_POS_INT_CON 0x38
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#define PMU_GPIO1_NEG_INT_CON 0x3c
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#define PMU_GPIO0_POS_INT_ST 0x40
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#define PMU_GPIO0_NEG_INT_ST 0x44
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#define PMU_GPIO1_POS_INT_ST 0x48
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#define PMU_GPIO1_NEG_INT_ST 0x4c
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#define PMU_PWRDN_INTEN 0x50
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#define PMU_PWRDN_STATUS 0x54
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#define PMU_WAKEUP_STATUS 0x58
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#define PMU_BUS_CLR 0x5c
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#define PMU_BUS_IDLE_REQ 0x60
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#define PMU_BUS_IDLE_ST 0x64
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#define PMU_BUS_IDLE_ACK 0x68
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#define PMU_CCI500_CON 0x6c
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#define PMU_ADB400_CON 0x70
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#define PMU_ADB400_ST 0x74
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#define PMU_POWER_ST 0x78
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#define PMU_CORE_PWR_ST 0x7c
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#define PMU_OSC_CNT 0x80
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#define PMU_PLLLOCK_CNT 0x84
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#define PMU_PLLRST_CNT 0x88
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#define PMU_STABLE_CNT 0x8c
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#define PMU_DDRIO_PWRON_CNT 0x90
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#define PMU_WAKEUP_RST_CLR_CNT 0x94
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#define PMU_DDR_SREF_ST 0x98
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#define PMU_SCU_L_PWRDN_CNT 0x9c
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#define PMU_SCU_L_PWRUP_CNT 0xa0
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#define PMU_SCU_B_PWRDN_CNT 0xa4
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#define PMU_SCU_B_PWRUP_CNT 0xa8
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#define PMU_GPU_PWRDN_CNT 0xac
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#define PMU_GPU_PWRUP_CNT 0xb0
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#define PMU_CENTER_PWRDN_CNT 0xb4
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#define PMU_CENTER_PWRUP_CNT 0xb8
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#define PMU_TIMEOUT_CNT 0xbc
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#define PMU_CPU0APM_CON 0xc0
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#define PMU_CPU1APM_CON 0xc4
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#define PMU_CPU2APM_CON 0xc8
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#define PMU_CPU3APM_CON 0xcc
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#define PMU_CPU0BPM_CON 0xd0
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#define PMU_CPU1BPM_CON 0xd4
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#define PMU_NOC_AUTO_ENA 0xd8
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#define PMU_PWRDN_CON1 0xdc
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#define PMUGRF_GPIO0A_IOMUX 0x00
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#define PMUGRF_GPIO1A_IOMUX 0x10
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#define PMUGRF_GPIO1C_IOMUX 0x18
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#define PMUGRF_GPIO0A6_IOMUX_SHIFT 12
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#define PMUGRF_GPIO0A6_IOMUX_PWM 0x1
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#define PMUGRF_GPIO1C3_IOMUX_SHIFT 6
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#define PMUGRF_GPIO1C3_IOMUX_PWM 0x1
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#define CPU_AXI_QOS_ID_COREID 0x00
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#define CPU_AXI_QOS_REVISIONID 0x04
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#define CPU_AXI_QOS_PRIORITY 0x08
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#define CPU_AXI_QOS_MODE 0x0c
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#define CPU_AXI_QOS_BANDWIDTH 0x10
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#define CPU_AXI_QOS_SATURATION 0x14
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#define CPU_AXI_QOS_EXTCONTROL 0x18
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#define CPU_AXI_QOS_NUM_REGS 0x07
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#define CPU_AXI_CCI_M0_QOS_BASE 0xffa50000
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#define CPU_AXI_CCI_M1_QOS_BASE 0xffad8000
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#define CPU_AXI_DMAC0_QOS_BASE 0xffa64200
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#define CPU_AXI_DMAC1_QOS_BASE 0xffa64280
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#define CPU_AXI_DCF_QOS_BASE 0xffa64180
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#define CPU_AXI_CRYPTO0_QOS_BASE 0xffa64100
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#define CPU_AXI_CRYPTO1_QOS_BASE 0xffa64080
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#define CPU_AXI_PMU_CM0_QOS_BASE 0xffa68000
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#define CPU_AXI_PERI_CM1_QOS_BASE 0xffa64300
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#define CPU_AXI_GIC_QOS_BASE 0xffa78000
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#define CPU_AXI_SDIO_QOS_BASE 0xffa76000
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#define CPU_AXI_SDMMC_QOS_BASE 0xffa74000
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#define CPU_AXI_EMMC_QOS_BASE 0xffa58000
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#define CPU_AXI_GMAC_QOS_BASE 0xffa5c000
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#define CPU_AXI_USB_OTG0_QOS_BASE 0xffa70000
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#define CPU_AXI_USB_OTG1_QOS_BASE 0xffa70080
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#define CPU_AXI_USB_HOST0_QOS_BASE 0xffa60100
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#define CPU_AXI_USB_HOST1_QOS_BASE 0xffa60180
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#define CPU_AXI_GPU_QOS_BASE 0xffae0000
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#define CPU_AXI_VIDEO_M0_QOS_BASE 0xffab8000
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#define CPU_AXI_VIDEO_M1_R_QOS_BASE 0xffac0000
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#define CPU_AXI_VIDEO_M1_W_QOS_BASE 0xffac0080
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#define CPU_AXI_RGA_R_QOS_BASE 0xffab0000
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#define CPU_AXI_RGA_W_QOS_BASE 0xffab0080
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#define CPU_AXI_IEP_QOS_BASE 0xffa98000
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#define CPU_AXI_VOP_BIG_R_QOS_BASE 0xffac8000
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#define CPU_AXI_VOP_BIG_W_QOS_BASE 0xffac8080
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#define CPU_AXI_VOP_LITTLE_QOS_BASE 0xffad0000
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#define CPU_AXI_ISP0_M0_QOS_BASE 0xffaa0000
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#define CPU_AXI_ISP0_M1_QOS_BASE 0xffaa0080
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#define CPU_AXI_ISP1_M0_QOS_BASE 0xffaa8000
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#define CPU_AXI_ISP1_M1_QOS_BASE 0xffaa8080
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#define CPU_AXI_HDCP_QOS_BASE 0xffa90000
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#define CPU_AXI_PERIHP_NSP_QOS_BASE 0xffad8080
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#define CPU_AXI_PERILP_NSP_QOS_BASE 0xffad8180
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#define CPU_AXI_PERILPSLV_NSP_QOS_BASE 0xffad8100
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#define GRF_GPIO2A_IOMUX 0xe000
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#define GRF_GPIO2B_IOMUX 0xe004
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#define GRF_GPIO2C_IOMUX 0xe008
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#define GRF_GPIO2D_IOMUX 0xe00c
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#define GRF_GPIO3A_IOMUX 0xe010
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#define GRF_GPIO3B_IOMUX 0xe014
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#define GRF_GPIO3C_IOMUX 0xe018
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#define GRF_GPIO3D_IOMUX 0xe01c
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#define GRF_GPIO4A_IOMUX 0xe020
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#define GRF_GPIO4B_IOMUX 0xe024
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#define GRF_GPIO4C_IOMUX 0xe028
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#define GRF_GPIO4D_IOMUX 0xe02c
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#define GRF_GPIO2A_P 0xe040
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#define GRF_GPIO2B_P 0xe044
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#define GRF_GPIO2C_P 0xe048
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#define GRF_GPIO2D_P 0xe04C
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#define GRF_GPIO3A_P 0xe050
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#define GRF_GPIO3B_P 0xe054
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#define GRF_GPIO3C_P 0xe058
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#define GRF_GPIO3D_P 0xe05C
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#define GRF_GPIO4A_P 0xe060
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#define GRF_GPIO4B_P 0xe064
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#define GRF_GPIO4C_P 0xe068
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#define GRF_GPIO4D_P 0xe06C
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#endif /* __PMU_REGS_H__ */
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