Add support for Cortex-A76AE CPU
Change-Id: I0a81f4ea94d41245cd5150de341b51fc70babffe Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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@ -1669,6 +1669,8 @@ The FVP models used are Version 11.5 Build 33, unless otherwise stated.
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- ``FVP_Base_Cortex-A73x4``
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- ``FVP_Base_Cortex-A73x4``
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- ``FVP_Base_Cortex-A75x4``
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- ``FVP_Base_Cortex-A75x4``
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- ``FVP_Base_Cortex-A76x4``
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- ``FVP_Base_Cortex-A76x4``
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- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
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- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
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- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
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- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
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- ``FVP_Base_Deimos``
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- ``FVP_Base_Deimos``
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
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@ -0,0 +1,25 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_A76AE_H
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#define CORTEX_A76AE_H
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#include <lib/utils_def.h>
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/* Cortex-A76AE MIDR for revision 0 */
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#define CORTEX_A76AE_MIDR U(0x410FD0E0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions.
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******************************************************************************/
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#define CORTEX_A76AE_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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/* Definitions of register field mask in CORTEX_A76AE_CPUPWRCTLR_EL1 */
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#define CORTEX_A76AE_CORE_PWRDN_EN_MASK U(0x1)
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#define CORTEX_A76AE_CPUECTLR_EL1 S3_0_C15_C1_4
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#endif /* CORTEX_A76AE_H */
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@ -0,0 +1,56 @@
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/*
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* Copyright (c) 2019, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <asm_macros.S>
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#include <cortex_a76ae.h>
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#include <cpu_macros.S>
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/* ---------------------------------------------
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* HW will do the cache maintenance while powering down
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* ---------------------------------------------
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*/
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func cortex_a76ae_core_pwr_dwn
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/* ---------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------
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*/
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mrs x0, CORTEX_A76AE_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_A76AE_CORE_PWRDN_EN_MASK
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msr CORTEX_A76AE_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_a76ae_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex-A76AE. Must follow AAPCS.
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*/
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func cortex_a76ae_errata_report
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ret
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endfunc cortex_a76ae_errata_report
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#endif /* REPORT_ERRATA */
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/* ---------------------------------------------
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* This function provides cortex_a76ae specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_a76ae_regs, "aS"
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cortex_a76ae_regs: /* The ASCII list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_a76ae_cpu_reg_dump
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adr x6, cortex_a76ae_regs
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mrs x8, CORTEX_A76AE_CPUECTLR_EL1
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ret
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endfunc cortex_a76ae_cpu_reg_dump
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declare_cpu_ops cortex_a76ae, CORTEX_A76AE_MIDR, CPU_NO_RESET_FUNC, \
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cortex_a76ae_core_pwr_dwn
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@ -103,6 +103,7 @@ FVP_CPU_LIBS += lib/cpus/aarch64/cortex_a35.S \
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lib/cpus/aarch64/cortex_a73.S \
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lib/cpus/aarch64/cortex_a73.S \
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lib/cpus/aarch64/cortex_a75.S \
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lib/cpus/aarch64/cortex_a75.S \
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lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a76.S \
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lib/cpus/aarch64/cortex_a76ae.S \
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/neoverse_n1.S \
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lib/cpus/aarch64/cortex_deimos.S \
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lib/cpus/aarch64/cortex_deimos.S \
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lib/cpus/aarch64/neoverse_zeus.S
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lib/cpus/aarch64/neoverse_zeus.S
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@ -185,6 +185,8 @@ The FVP models used are Version 11.5 Build 33, unless otherwise stated.
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- ``FVP_Base_Cortex-A73x4``
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- ``FVP_Base_Cortex-A73x4``
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- ``FVP_Base_Cortex-A75x4``
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- ``FVP_Base_Cortex-A75x4``
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- ``FVP_Base_Cortex-A76x4``
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- ``FVP_Base_Cortex-A76x4``
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- ``FVP_Base_Cortex-A76AEx4`` (Tested with internal model)
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- ``FVP_Base_Cortex-A76AEx8`` (Tested with internal model)
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- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
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- ``FVP_Base_Neoverse-N1x4`` (Tested with internal model)
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- ``FVP_Base_Deimos``
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- ``FVP_Base_Deimos``
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
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- ``FVP_CSS_SGI-575`` (Version 11.3 build 42)
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