SPMD: enhance SPMC internal boot states
This patch adds SPMC states used by the SPMD to track SPMC boot phases specifically on secondary cores. Change-Id: If97af7352dda7f04a8e46a56892a2aeddcfab91b Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
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@ -133,9 +133,18 @@ static int32_t spmd_init(void)
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{
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spmd_spm_core_context_t *ctx = spmd_get_context();
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uint64_t rc;
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unsigned int linear_id = plat_my_core_pos();
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unsigned int core_id;
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VERBOSE("SPM Core init start.\n");
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ctx->state = SPMC_STATE_RESET;
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ctx->state = SPMC_STATE_ON_PENDING;
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/* Set the SPMC context state on other CPUs to OFF */
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for (core_id = 0; core_id < PLATFORM_CORE_COUNT; core_id++) {
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if (core_id != linear_id) {
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spm_core_context[core_id].state = SPMC_STATE_OFF;
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}
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}
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rc = spmd_spm_core_sync_entry(ctx);
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if (rc != 0ULL) {
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@ -143,7 +152,8 @@ static int32_t spmd_init(void)
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return 0;
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}
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ctx->state = SPMC_STATE_IDLE;
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ctx->state = SPMC_STATE_ON;
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VERBOSE("SPM Core init end.\n");
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return 1;
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@ -375,7 +385,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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* this CPU. If so, then indicate that the SPM Core initialised
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* unsuccessfully.
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*/
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if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
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if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
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spmd_spm_core_sync_exit(x2);
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}
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@ -508,7 +518,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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* this CPU from the Secure world. If so, then indicate that the
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* SPM Core initialised successfully.
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*/
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if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
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if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
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spmd_spm_core_sync_exit(0);
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}
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@ -35,7 +35,9 @@
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typedef enum spmc_state {
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SPMC_STATE_RESET = 0,
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SPMC_STATE_IDLE
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SPMC_STATE_OFF,
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SPMC_STATE_ON_PENDING,
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SPMC_STATE_ON
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} spmc_state_t;
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/*
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