SPMD: enhance SPMC internal boot states

This patch adds SPMC states used by the SPMD to track SPMC boot phases
specifically on secondary cores.

Change-Id: If97af7352dda7f04a8e46a56892a2aeddcfab91b
Signed-off-by: Olivier Deprez <olivier.deprez@arm.com>
Signed-off-by: Max Shvetsov <maksims.svecovs@arm.com>
This commit is contained in:
Olivier Deprez 2019-10-28 09:03:13 +00:00 committed by Max Shvetsov
parent c0267cc994
commit 9dcf63dd8b
2 changed files with 17 additions and 5 deletions

View File

@ -133,9 +133,18 @@ static int32_t spmd_init(void)
{
spmd_spm_core_context_t *ctx = spmd_get_context();
uint64_t rc;
unsigned int linear_id = plat_my_core_pos();
unsigned int core_id;
VERBOSE("SPM Core init start.\n");
ctx->state = SPMC_STATE_RESET;
ctx->state = SPMC_STATE_ON_PENDING;
/* Set the SPMC context state on other CPUs to OFF */
for (core_id = 0; core_id < PLATFORM_CORE_COUNT; core_id++) {
if (core_id != linear_id) {
spm_core_context[core_id].state = SPMC_STATE_OFF;
}
}
rc = spmd_spm_core_sync_entry(ctx);
if (rc != 0ULL) {
@ -143,7 +152,8 @@ static int32_t spmd_init(void)
return 0;
}
ctx->state = SPMC_STATE_IDLE;
ctx->state = SPMC_STATE_ON;
VERBOSE("SPM Core init end.\n");
return 1;
@ -375,7 +385,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
* this CPU. If so, then indicate that the SPM Core initialised
* unsuccessfully.
*/
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
spmd_spm_core_sync_exit(x2);
}
@ -508,7 +518,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
* this CPU from the Secure world. If so, then indicate that the
* SPM Core initialised successfully.
*/
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
spmd_spm_core_sync_exit(0);
}

View File

@ -35,7 +35,9 @@
typedef enum spmc_state {
SPMC_STATE_RESET = 0,
SPMC_STATE_IDLE
SPMC_STATE_OFF,
SPMC_STATE_ON_PENDING,
SPMC_STATE_ON
} spmc_state_t;
/*