Merge "stm32mp1: allow non-secure access to reset upon periph registration" into integration
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commit
9eed56e871
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@ -233,6 +233,26 @@ void stm32mp_register_non_secure_periph(enum stm32mp_shres id)
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register_periph(id, SHRES_NON_SECURE);
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register_periph(id, SHRES_NON_SECURE);
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}
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}
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static bool stm32mp_gpio_bank_is_non_secure(unsigned int bank)
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{
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unsigned int non_secure = 0U;
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unsigned int i;
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lock_registering();
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if (bank != GPIO_BANK_Z) {
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return true;
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}
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for (i = 0U; i < get_gpioz_nbpin(); i++) {
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if (periph_is_non_secure(STM32MP1_SHRES_GPIOZ(i))) {
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non_secure++;
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}
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}
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return non_secure == get_gpioz_nbpin();
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}
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static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
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static bool stm32mp_gpio_bank_is_secure(unsigned int bank)
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{
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{
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unsigned int secure = 0U;
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unsigned int secure = 0U;
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@ -312,10 +332,46 @@ bool stm32mp_nsec_can_access_clock(unsigned long clock_id)
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return periph_is_non_secure(shres_id);
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return periph_is_non_secure(shres_id);
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}
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}
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/* Currently allow full access by non-secure to platform reset services */
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
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bool stm32mp_nsec_can_access_reset(unsigned int reset_id)
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{
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{
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return true;
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enum stm32mp_shres shres_id = STM32MP1_SHRES_COUNT;
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switch (reset_id) {
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case CRYP1_R:
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shres_id = STM32MP1_SHRES_CRYP1;
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break;
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case GPIOZ_R:
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/* GPIOZ reset mandates all pins are non-secure */
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return stm32mp_gpio_bank_is_non_secure(GPIO_BANK_Z);
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case HASH1_R:
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shres_id = STM32MP1_SHRES_HASH1;
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break;
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case I2C4_R:
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shres_id = STM32MP1_SHRES_I2C4;
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break;
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case I2C6_R:
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shres_id = STM32MP1_SHRES_I2C6;
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break;
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case MCU_R:
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shres_id = STM32MP1_SHRES_MCU;
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break;
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case MDMA_R:
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shres_id = STM32MP1_SHRES_MDMA;
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break;
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case RNG1_R:
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shres_id = STM32MP1_SHRES_RNG1;
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break;
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case SPI6_R:
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shres_id = STM32MP1_SHRES_SPI6;
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break;
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case USART1_R:
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shres_id = STM32MP1_SHRES_USART1;
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break;
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default:
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return false;
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}
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return periph_is_non_secure(shres_id);
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}
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}
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static bool mckprot_protects_periph(enum stm32mp_shres id)
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static bool mckprot_protects_periph(enum stm32mp_shres id)
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