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cpus: denver: disable DCO operations from platform code 

This patch moves the code to disable DCO operations out from common
CPU files. This allows the platform code to call thsi API as and
when required. There are certain CPU power down states which require
the DCO to be kept ON and platforms can decide selectively now.

Change-Id: Icb946fe2545a7d8c5903c420d1ee169c4921a2d1
Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
This commit is contained in:
Varun Wadekar 2016-02-22 11:09:41 -08:00
parent 990c1e0113
commit 9f1c5dd19b
3 changed files with 22 additions and 19 deletions
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9
include/lib/cpus/aarch64/denver.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -44,4 +44,11 @@
/* CPU state ids - implementation defined */
#define DENVER_CPU_STATE_POWER_DOWN 0x3
#ifndef __ASSEMBLY__
/* Disable Dynamic Code Optimisation */
void denver_disable_dco(void);
#endif
#endif /* __DENVER_H__ */

20
lib/cpus/aarch64/denver.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2016, ARM Limited and Contributors. All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
@ -35,6 +35,8 @@
#include <cpu_macros.S>
#include <plat_macros.S>
.global denver_disable_dco
/* ---------------------------------------------
* Disable debug interfaces
* ---------------------------------------------
@ -111,22 +113,6 @@ func denver_core_pwr_dwn
mov x19, x30
/* ----------------------------------------------------
* We enter the 'core power gated with ARM state not
* retained' power state during CPU power down. We let
* DCO know that we expect to enter this power state
* by writing to the ACTLR_EL1 register.
* ----------------------------------------------------
*/
mov x0, #DENVER_CPU_STATE_POWER_DOWN
msr actlr_el1, x0
/* ---------------------------------------------
* Force DCO to be quiescent
* ---------------------------------------------
*/
bl denver_disable_dco
/* ---------------------------------------------
* Force the debug interfaces to be quiescent
* ---------------------------------------------

12
plat/nvidia/tegra/soc/t132/plat_psci_handlers.c
View File

@ -110,6 +110,13 @@ int tegra_soc_pwr_domain_on(u_register_t mpidr)
int tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
{
tegra_fc_cpu_off(read_mpidr() & MPIDR_CPU_MASK);
/* Disable DCO operations */
denver_disable_dco();
/* Power down the CPU */
write_actlr_el1(DENVER_CPU_STATE_POWER_DOWN);
return PSCI_E_SUCCESS;
}
@ -128,7 +135,10 @@ int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
/* Program FC to enter suspend state */
tegra_fc_cpu_powerdn(read_mpidr());
/* Suspend DCO operations */
/* Disable DCO operations */
denver_disable_dco();
/* Program the suspend state ID */
write_actlr_el1(target_state->pwr_domain_state[PLAT_MAX_PWR_LVL]);
return PSCI_E_SUCCESS;