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Merge pull request #1211 from Leo-Yan/remove_ca73_cpu_nap_state 

Hikey960: Remove ca73 cpu nap state
This commit is contained in:
davidcunado-arm 2018-01-17 17:34:29 +00:00 committed by GitHub
parent 1c10d96fc3 4c8a5787d2
commit 9fd4a36c40
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GPG Key ID: 4AEE18F83AFDEB23
3 changed files with 29 additions and 97 deletions
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31
plat/hisilicon/hikey960/aarch64/hikey960_helpers.S
View File

@ -16,8 +16,6 @@
.globl plat_crash_console_putc
.globl plat_report_exception
.globl plat_reset_handler
.globl set_retention_ticks
.globl clr_retention_ticks
.globl clr_ex
.globl nop
@ -138,35 +136,6 @@ func plat_reset_handler
ret
endfunc plat_reset_handler
/* -----------------------------------------------------
* void set_retention_ticks(unsigned int val);
* Clobber list : x0
* -----------------------------------------------------
*/
func set_retention_ticks
mrs x0, CORTEX_A53_ECTLR_EL1
bic x0, x0, #CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK
orr x0, x0, #RETENTION_ENTRY_TICKS_8
msr CORTEX_A53_ECTLR_EL1, x0
isb
dsb sy
ret
endfunc set_retention_ticks
/* -----------------------------------------------------
* void clr_retention_ticks(unsigned int val);
* Clobber list : x0
* -----------------------------------------------------
*/
func clr_retention_ticks
mrs x0, CORTEX_A53_ECTLR_EL1
bic x0, x0, #CORTEX_A53_ECTLR_CPU_RET_CTRL_MASK
msr CORTEX_A53_ECTLR_EL1, x0
isb
dsb sy
ret
endfunc clr_retention_ticks
/* -----------------------------------------------------
* void clrex(void);
* -----------------------------------------------------

89
plat/hisilicon/hikey960/hikey960_pm.c
View File

@ -26,38 +26,6 @@
#define SYSTEM_PWR_STATE(state) \
((state)->pwr_domain_state[PLAT_MAX_PWR_LVL])
#define PSTATE_WIDTH 4
#define PSTATE_MASK ((1 << PSTATE_WIDTH) - 1)
#define MAKE_PWRSTATE(lvl2_state, lvl1_state, lvl0_state, pwr_lvl, type) \
(((lvl2_state) << (PSTATE_ID_SHIFT + PSTATE_WIDTH * 2)) | \
((lvl1_state) << (PSTATE_ID_SHIFT + PSTATE_WIDTH)) | \
((lvl0_state) << (PSTATE_ID_SHIFT)) | \
((pwr_lvl) << PSTATE_PWR_LVL_SHIFT) | \
((type) << PSTATE_TYPE_SHIFT))
/*
* The table storing the valid idle power states. Ensure that the
* array entries are populated in ascending order of state-id to
* enable us to use binary search during power state validation.
* The table must be terminated by a NULL entry.
*/
const unsigned int hikey960_pwr_idle_states[] = {
/* State-id - 0x001 */
MAKE_PWRSTATE(PLAT_MAX_RUN_STATE, PLAT_MAX_RUN_STATE,
PLAT_MAX_STB_STATE, MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
/* State-id - 0x002 */
MAKE_PWRSTATE(PLAT_MAX_RUN_STATE, PLAT_MAX_RUN_STATE,
PLAT_MAX_RET_STATE, MPIDR_AFFLVL0, PSTATE_TYPE_STANDBY),
/* State-id - 0x003 */
MAKE_PWRSTATE(PLAT_MAX_RUN_STATE, PLAT_MAX_RUN_STATE,
PLAT_MAX_OFF_STATE, MPIDR_AFFLVL0, PSTATE_TYPE_POWERDOWN),
/* State-id - 0x033 */
MAKE_PWRSTATE(PLAT_MAX_RUN_STATE, PLAT_MAX_OFF_STATE,
PLAT_MAX_OFF_STATE, MPIDR_AFFLVL1, PSTATE_TYPE_POWERDOWN),
0,
};
#define DMAC_GLB_REG_SEC 0x694
#define AXI_CONF_BASE 0x820
@ -66,24 +34,17 @@ static uintptr_t hikey960_sec_entrypoint;
static void hikey960_pwr_domain_standby(plat_local_state_t cpu_state)
{
unsigned long scr;
unsigned int val = 0;
assert(cpu_state == PLAT_MAX_STB_STATE ||
cpu_state == PLAT_MAX_RET_STATE);
scr = read_scr_el3();
/* Enable Physical IRQ and FIQ to wake the CPU*/
/* Enable Physical IRQ and FIQ to wake the CPU */
write_scr_el3(scr | SCR_IRQ_BIT | SCR_FIQ_BIT);
if (cpu_state == PLAT_MAX_RET_STATE)
set_retention_ticks(val);
/* Add barrier before CPU enter WFI state */
isb();
dsb();
wfi();
if (cpu_state == PLAT_MAX_RET_STATE)
clr_retention_ticks(val);
/*
* Restore SCR to the original value, synchronisazion of
* scr_el3 is done by eret while el3_exit to save some
@ -161,34 +122,38 @@ static void __dead2 hikey960_system_reset(void)
int hikey960_validate_power_state(unsigned int power_state,
psci_power_state_t *req_state)
{
unsigned int state_id;
unsigned int pstate = psci_get_pstate_type(power_state);
unsigned int pwr_lvl = psci_get_pstate_pwrlvl(power_state);
int i;
assert(req_state);
/*
* Currently we are using a linear search for finding the matching
* entry in the idle power state array. This can be made a binary
* search if the number of entries justify the additional complexity.
*/
for (i = 0; !!hikey960_pwr_idle_states[i]; i++) {
if (power_state == hikey960_pwr_idle_states[i])
break;
}
/* Return error if entry not found in the idle state array */
if (!hikey960_pwr_idle_states[i])
if (pwr_lvl > PLAT_MAX_PWR_LVL)
return PSCI_E_INVALID_PARAMS;
i = 0;
state_id = psci_get_pstate_id(power_state);
/* Sanity check the requested state */
if (pstate == PSTATE_TYPE_STANDBY) {
/*
* It's possible to enter standby only on power level 0
* Ignore any other power level.
*/
if (pwr_lvl != MPIDR_AFFLVL0)
return PSCI_E_INVALID_PARAMS;
/* Parse the State ID and populate the state info parameter */
while (state_id) {
req_state->pwr_domain_state[i++] = state_id & PSTATE_MASK;
state_id >>= PSTATE_WIDTH;
req_state->pwr_domain_state[MPIDR_AFFLVL0] =
PLAT_MAX_RET_STATE;
} else {
for (i = MPIDR_AFFLVL0; i <= pwr_lvl; i++)
req_state->pwr_domain_state[i] =
PLAT_MAX_OFF_STATE;
}
/*
* We expect the 'state id' to be zero.
*/
if (psci_get_pstate_id(power_state))
return PSCI_E_INVALID_PARAMS;
return PSCI_E_SUCCESS;
}

6
plat/hisilicon/hikey960/include/platform_def.h
View File

@ -31,10 +31,8 @@
#define PLAT_NUM_PWR_DOMAINS (PLATFORM_CORE_COUNT + \
PLATFORM_CLUSTER_COUNT + 1)
#define PLAT_MAX_RUN_STATE 0
#define PLAT_MAX_STB_STATE 1
#define PLAT_MAX_RET_STATE 2
#define PLAT_MAX_OFF_STATE 3
#define PLAT_MAX_RET_STATE 1
#define PLAT_MAX_OFF_STATE 2
#define MAX_IO_DEVICES 3
#define MAX_IO_HANDLES 4