Tegra: restrict non-secure PMC accesses
Platforms that do not support bpmp firmware, do not need access to the PMC block from outside of the CPU complex. The agents running on the CPU can always access the PMC through the EL3 exception space. This patch restricts non-secure world access to the PMC block on such platforms. Change-Id: I2c4318dc07ddf6407c1700595e0f4aac377ba258 Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -175,6 +175,8 @@
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******************************************************************************/
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#define TEGRA_MISC_BASE U(0x70000000)
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#define HARDWARE_REVISION_OFFSET U(0x804)
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#define APB_SLAVE_SECURITY_ENABLE U(0xC00)
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#define PMC_SECURITY_EN_BIT (U(1) << 13)
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#define PINMUX_AUX_DVFS_PWM U(0x3184)
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#define PINMUX_PWM_TRISTATE (U(1) << 4)
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@ -473,6 +473,11 @@ int tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
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offset = plat_params->tzdram_base - plat_params->sc7entry_fw_base;
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tegra_memctrl_tzdram_setup(plat_params->sc7entry_fw_base,
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plat_params->tzdram_size + offset);
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/* restrict PMC access to secure world */
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val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
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val |= PMC_SECURITY_EN_BIT;
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mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
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}
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}
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@ -157,6 +157,7 @@ void plat_late_platform_setup(void)
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const plat_params_from_bl2_t *plat_params = bl31_get_plat_params();
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uint64_t sc7entry_end, offset;
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int ret;
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uint32_t val;
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/* memmap TZDRAM area containing the SC7 Entry Firmware */
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if (plat_params->sc7entry_fw_base && plat_params->sc7entry_fw_size) {
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@ -193,6 +194,11 @@ void plat_late_platform_setup(void)
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plat_params->sc7entry_fw_size,
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MT_SECURE | MT_RO_DATA);
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assert(ret == 0);
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/* restrict PMC access to secure world */
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val = mmio_read_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE);
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val |= PMC_SECURITY_EN_BIT;
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mmio_write_32(TEGRA_MISC_BASE + APB_SLAVE_SECURITY_ENABLE, val);
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}
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}
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