From a078134e2305ca5695731bc275a5ca892cc38880 Mon Sep 17 00:00:00 2001 From: Yann Gautier Date: Tue, 7 Sep 2021 09:07:35 +0200 Subject: [PATCH] fix(st-ddr): correct DDR warnings Replace %d with %u in logs, to avoid warning when -Wformat-signedness is enabled. And correct the order of includes. Change-Id: I7c711a37fc1deceb8853831a8a09ae50422859c9 Signed-off-by: Yann Gautier --- drivers/st/ddr/stm32mp1_ddr.c | 10 +++++----- drivers/st/ddr/stm32mp1_ram.c | 13 ++++++------- 2 files changed, 11 insertions(+), 12 deletions(-) diff --git a/drivers/st/ddr/stm32mp1_ddr.c b/drivers/st/ddr/stm32mp1_ddr.c index 3db47c4fd..3294f6e3e 100644 --- a/drivers/st/ddr/stm32mp1_ddr.c +++ b/drivers/st/ddr/stm32mp1_ddr.c @@ -1,5 +1,5 @@ /* - * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ @@ -7,21 +7,21 @@ #include #include -#include - #include #include #include #include #include -#include #include #include #include #include +#include #include #include +#include + struct reg_desc { const char *name; uint16_t offset; /* Offset for base address */ @@ -729,7 +729,7 @@ void stm32mp1_ddr_init(struct ddr_info *priv, } VERBOSE("name = %s\n", config->info.name); - VERBOSE("speed = %d kHz\n", config->info.speed); + VERBOSE("speed = %u kHz\n", config->info.speed); VERBOSE("size = 0x%x\n", config->info.size); /* DDR INIT SEQUENCE */ diff --git a/drivers/st/ddr/stm32mp1_ram.c b/drivers/st/ddr/stm32mp1_ram.c index 064e3180e..f1e34255f 100644 --- a/drivers/st/ddr/stm32mp1_ram.c +++ b/drivers/st/ddr/stm32mp1_ram.c @@ -1,15 +1,11 @@ /* - * Copyright (C) 2018-2021, STMicroelectronics - All Rights Reserved + * Copyright (C) 2018-2022, STMicroelectronics - All Rights Reserved * * SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause */ #include -#include - -#include - #include #include #include @@ -18,6 +14,9 @@ #include #include #include +#include + +#include #define DDR_PATTERN 0xAAAAAAAAU #define DDR_ANTIPATTERN 0x55555555U @@ -32,7 +31,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) ddrphy_clk = clk_get_rate(DDRPHYC); - VERBOSE("DDR: mem_speed (%d kHz), RCC %ld kHz\n", + VERBOSE("DDR: mem_speed (%u kHz), RCC %lu kHz\n", mem_speed, ddrphy_clk / 1000U); mem_speed_hz = mem_speed * 1000U; @@ -44,7 +43,7 @@ int stm32mp1_ddr_clk_enable(struct ddr_info *priv, uint32_t mem_speed) ddr_clk = mem_speed_hz - ddrphy_clk; } if (ddr_clk > (mem_speed_hz / 10)) { - ERROR("DDR expected freq %d kHz, current is %ld kHz\n", + ERROR("DDR expected freq %u kHz, current is %lu kHz\n", mem_speed, ddrphy_clk / 1000U); return -1; }