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Tegra194: memctrl: Disable PVARDC coalescer 

Due to a hardware bug PVA may perform memory transactions which
cause coalescer faults. This change works around the issue by
disabling coalescer for PVA0RDC and PVA1RDC.

Change-Id: I27d1f6e7bc819fb303dae98079d9277fa346a1d3
Signed-off-by: Arto Merilainen <amerilainen@nvidia.com>
This commit is contained in:
Arto Merilainen 2018-01-18 19:47:36 +02:00 committed by Varun Wadekar
parent 21e22fe301
commit a0cacc955a
2 changed files with 13 additions and 1 deletions
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5
plat/nvidia/tegra/include/t194/tegra_mc_def.h
View File

@ -531,7 +531,10 @@
#define MC_CLIENT_HOTRESET_STATUS2 0x1898U
#define MC_COALESCE_CTRL 0x2930U
#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31)
#define MC_COALESCE_CTRL_COALESCER_ENABLE (1U << 31)
#define MC_COALESCE_CONFIG_6_0 0x294cU
#define MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED (1U << 8)
#define MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED (1U << 14)
/*******************************************************************************
* Tegra TSA Controller constants

9
plat/nvidia/tegra/soc/t194/plat_memctrl.c
View File

@ -618,6 +618,15 @@ static void tegra194_memctrl_reconfig_mss_clients(void)
reg_val = MC_COALESCE_CTRL_COALESCER_ENABLE;
tegra_mc_write_32(MC_COALESCE_CTRL, reg_val);
/*
* WAR to hardware bug 1953865: Coalescer must be disabled
* for PVA0RDC and PVA1RDC interfaces.
*/
reg_val = tegra_mc_read_32(MC_COALESCE_CONFIG_6_0);
reg_val &= ~(MC_COALESCE_CONFIG_6_0_PVA0RDC_COALESCER_ENABLED |
MC_COALESCE_CONFIG_6_0_PVA1RDC_COALESCER_ENABLED);
tegra_mc_write_32(MC_COALESCE_CONFIG_6_0, reg_val);
}
/*******************************************************************************