rockchip/rk3399: disable more powerdomain prepare for shutdown logic rail
Change-Id: Ia59adf48cf14eb627721264765bce50cb31065ef Signed-off-by: Lin Huang <hl@rock-chips.com>
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@ -336,6 +336,11 @@ static void pmu_power_domains_suspend(void)
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pmu_set_power_domain(PD_RGA, pmu_pd_off);
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pmu_set_power_domain(PD_VCODEC, pmu_pd_off);
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pmu_set_power_domain(PD_VDU, pmu_pd_off);
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pmu_set_power_domain(PD_USB3, pmu_pd_off);
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pmu_set_power_domain(PD_EMMC, pmu_pd_off);
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pmu_set_power_domain(PD_VIO, pmu_pd_off);
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pmu_set_power_domain(PD_SD, pmu_pd_off);
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pmu_set_power_domain(PD_PERIHP, pmu_pd_off);
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clk_gate_con_restore();
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}
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@ -371,6 +376,16 @@ static void pmu_power_domains_resume(void)
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pmu_set_power_domain(PD_TCPD0, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_GPU)))
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pmu_set_power_domain(PD_GPU, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_USB3)))
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pmu_set_power_domain(PD_USB3, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_EMMC)))
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pmu_set_power_domain(PD_EMMC, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_VIO)))
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pmu_set_power_domain(PD_VIO, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_SD)))
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pmu_set_power_domain(PD_SD, pmu_pd_on);
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if (!(pmu_powerdomain_state & BIT(PD_PERIHP)))
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pmu_set_power_domain(PD_PERIHP, pmu_pd_on);
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qos_restore();
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clk_gate_con_restore();
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}
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@ -828,6 +843,7 @@ static void sys_slp_config(void)
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BIT_WITH_WMSK(PMU_CLR_GIC2_CORE_L_HW));
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slp_mode_cfg = BIT(PMU_PWR_MODE_EN) |
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BIT(PMU_INPUT_CLAMP_EN) |
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BIT(PMU_POWER_OFF_REQ_CFG) |
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BIT(PMU_CPU0_PD_EN) |
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BIT(PMU_L2_FLUSH_EN) |
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@ -841,7 +857,9 @@ static void sys_slp_config(void)
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BIT(PMU_DDRC0_GATING_EN) |
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BIT(PMU_DDRC1_GATING_EN) |
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BIT(PMU_DDRIO0_RET_EN) |
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BIT(PMU_DDRIO0_RET_DE_REQ) |
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BIT(PMU_DDRIO1_RET_EN) |
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BIT(PMU_DDRIO1_RET_DE_REQ) |
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BIT(PMU_DDRIO_RET_HW_DE_REQ) |
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BIT(PMU_CENTER_PD_EN) |
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BIT(PMU_PERILP_PD_EN) |
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@ -1323,7 +1341,7 @@ int rockchip_soc_sys_pwr_dm_suspend(void)
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BIT(PMU_CLR_PERILP) |
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BIT(PMU_CLR_PERILPM0) |
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BIT(PMU_CLR_GIC));
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set_pmu_rsthold();
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sys_slp_config();
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m0_configure_suspend();
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@ -1449,7 +1467,7 @@ int rockchip_soc_sys_pwr_dm_resume(void)
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pmu_power_domains_resume();
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restore_abpll();
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restore_pmu_rsthold();
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clr_hw_idle(BIT(PMU_CLR_CENTER1) |
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BIT(PMU_CLR_ALIVE) |
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BIT(PMU_CLR_MSCH0) |
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@ -224,6 +224,47 @@ static void _pll_resume(uint32_t pll_id)
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set_pll_normal_mode(pll_id);
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}
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void set_pmu_rsthold(void)
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{
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uint32_t rstnhold_cofig0;
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uint32_t rstnhold_cofig1;
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slp_data.pmucru_rstnhold_con0 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON0);
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slp_data.pmucru_rstnhold_con1 = mmio_read_32(PMUCRU_BASE +
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PMUCRU_RSTNHOLD_CON1);
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rstnhold_cofig0 = BIT_WITH_WMSK(PRESETN_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_INTMEM_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(HRESETN_CM0S_NOC_PMU_HOLD) |
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BIT_WITH_WMSK(DRESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(POESETN_CM0S_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_TIMER_PMU_0_1_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_0_HOLD) |
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BIT_WITH_WMSK(RESETN_TIMER_PMU_1_HOLD) |
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BIT_WITH_WMSK(PRESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(RESETN_UART_M0_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_WDT_PMU_HOLD);
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rstnhold_cofig1 = BIT_WITH_WMSK(PRESETN_RKPWM_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PMUGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_SGRF_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO0_HOLD) |
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BIT_WITH_WMSK(PRESETN_GPIO1_HOLD) |
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BIT_WITH_WMSK(PRESETN_CRU_PMU_HOLD) |
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BIT_WITH_WMSK(PRESETN_PVTM_PMU_HOLD);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0, rstnhold_cofig0);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1, rstnhold_cofig1);
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}
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void restore_pmu_rsthold(void)
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{
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON0,
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slp_data.pmucru_rstnhold_con0 | REG_SOC_WMSK);
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mmio_write_32(PMUCRU_BASE + PMUCRU_RSTNHOLD_CON1,
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slp_data.pmucru_rstnhold_con1 | REG_SOC_WMSK);
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}
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/**
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* enable_dvfs_plls - To resume the specific PLLs
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*
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@ -56,6 +56,43 @@
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#define PMUCRU_GATE_CON(n) (0x100 + (n) * 4)
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#define CRU_GATE_CON(n) (0x300 + (n) * 4)
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#define PMUCRU_RSTNHOLD_CON0 0x120
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enum {
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PRESETN_NOC_PMU_HOLD = 1,
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PRESETN_INTMEM_PMU_HOLD,
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HRESETN_CM0S_PMU_HOLD,
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HRESETN_CM0S_NOC_PMU_HOLD,
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DRESETN_CM0S_PMU_HOLD,
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POESETN_CM0S_PMU_HOLD,
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PRESETN_SPI3_HOLD,
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RESETN_SPI3_HOLD,
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PRESETN_TIMER_PMU_0_1_HOLD,
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RESETN_TIMER_PMU_0_HOLD,
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RESETN_TIMER_PMU_1_HOLD,
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PRESETN_UART_M0_PMU_HOLD,
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RESETN_UART_M0_PMU_HOLD,
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PRESETN_WDT_PMU_HOLD
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};
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#define PMUCRU_RSTNHOLD_CON1 0x124
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enum {
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PRESETN_I2C0_HOLD,
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PRESETN_I2C4_HOLD,
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PRESETN_I2C8_HOLD,
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PRESETN_MAILBOX_PMU_HOLD,
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PRESETN_RKPWM_PMU_HOLD,
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PRESETN_PMUGRF_HOLD,
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PRESETN_SGRF_HOLD,
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PRESETN_GPIO0_HOLD,
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PRESETN_GPIO1_HOLD,
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PRESETN_CRU_PMU_HOLD,
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PRESETN_INTR_ARB_HOLD,
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PRESETN_PVTM_PMU_HOLD,
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RESETN_I2C0_HOLD,
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RESETN_I2C4_HOLD,
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RESETN_I2C8_HOLD
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};
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enum plls_id {
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ALPLL_ID = 0,
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ABPLL_ID,
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@ -97,6 +134,8 @@ struct deepsleep_data_s {
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uint32_t plls_con[END_PLL_ID][PLL_CON_COUNT];
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uint32_t cru_gate_con[CRU_GATE_COUNT];
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uint32_t pmucru_gate_con[PMUCRU_GATE_COUNT];
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uint32_t pmucru_rstnhold_con0;
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uint32_t pmucru_rstnhold_con1;
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};
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/**************************************************
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@ -256,5 +295,6 @@ void restore_abpll(void);
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void clk_gate_con_save(void);
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void clk_gate_con_disable(void);
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void clk_gate_con_restore(void);
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void set_pmu_rsthold(void);
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void restore_pmu_rsthold(void);
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#endif /* __SOC_H__ */
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