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Merge "mediatek: mt8192: devapc: Add devapc driver" into integration

This commit is contained in:
Madhukar Pappireddy 2021-04-22 16:19:16 +02:00 committed by TrustedFirmware Code Review
parent a05b3ad026 6b822d494f
commit a262546fc4
5 changed files with 3084 additions and 20 deletions
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4
plat/mediatek/mt8192/bl31_plat_setup.c
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@ -16,6 +16,7 @@
#include <lib/coreboot.h>
/* Platform Includes */
#include <devapc/devapc.h>
#include <emi_mpu/emi_mpu.h>
#include <gpio/mtgpio.h>
#include <mt_gic_v3.h>
@ -94,6 +95,9 @@ void bl31_platform_setup(void)
/* MPU Init */
emi_mpu_init();
/* DAPC Init */
devapc_init();
/* Initialize the GIC driver, CPU and distributor interfaces */
mt_gic_driver_init();
mt_gic_init();

2843
plat/mediatek/mt8192/drivers/devapc/devapc.c Normal file
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211
plat/mediatek/mt8192/drivers/devapc/devapc.h Normal file
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@ -0,0 +1,211 @@
/*
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
#ifndef DEVAPC_H
#define DEVAPC_H
#include <stdint.h>
#include <platform_def.h>
/******************************************************************************
* FUNCTION DEFINITION
******************************************************************************/
void devapc_init(void);
/******************************************************************************
* STRUCTURE DEFINITION
******************************************************************************/
enum DEVAPC_PERM_TYPE {
NO_PROTECTION = 0,
SEC_RW_ONLY,
SEC_RW_NS_R,
FORBIDDEN,
PERM_NUM,
};
enum DOMAIN_ID {
DOMAIN_0 = 0,
DOMAIN_1,
DOMAIN_2,
DOMAIN_3,
DOMAIN_4,
DOMAIN_5,
DOMAIN_6,
DOMAIN_7,
DOMAIN_8,
DOMAIN_9,
DOMAIN_10,
DOMAIN_11,
DOMAIN_12,
DOMAIN_13,
DOMAIN_14,
DOMAIN_15,
};
/* Slave Type */
enum DEVAPC_SLAVE_TYPE_SIMPLE {
SLAVE_TYPE_INFRA = 0,
SLAVE_TYPE_PERI,
SLAVE_TYPE_PERI2,
SLAVE_TYPE_PERI_PAR,
};
enum DEVAPC_SYS_INDEX {
DEVAPC_SYS0 = 0,
DEVAPC_SYS1,
DEVAPC_SYS2,
};
enum DEVAPC_SLAVE_TYPE {
SLAVE_TYPE_INFRA_AO_SYS0 = 0,
SLAVE_TYPE_INFRA_AO_SYS1,
SLAVE_TYPE_INFRA_AO_SYS2,
SLAVE_TYPE_PERI_AO_SYS0,
SLAVE_TYPE_PERI_AO_SYS1,
SLAVE_TYPE_PERI_AO_SYS2,
SLAVE_TYPE_PERI_AO2_SYS0,
SLAVE_TYPE_PERI_PAR_AO_SYS0,
};
/* Slave Num */
enum DEVAPC_SLAVE_NUM {
SLAVE_NUM_INFRA_AO_SYS0 = 23,
SLAVE_NUM_INFRA_AO_SYS1 = 256,
SLAVE_NUM_INFRA_AO_SYS2 = 70,
SLAVE_NUM_PERI_AO_SYS0 = 105,
SLAVE_NUM_PERI_AO_SYS1 = 66,
SLAVE_NUM_PERI_AO_SYS2 = 1,
SLAVE_NUM_PERI_AO2_SYS0 = 115,
SLAVE_NUM_PERI_PAR_AO_SYS0 = 27,
};
enum DEVAPC_SYS_DOM_NUM {
DOM_NUM_INFRA_AO_SYS0 = 16,
DOM_NUM_INFRA_AO_SYS1 = 4,
DOM_NUM_INFRA_AO_SYS2 = 4,
DOM_NUM_PERI_AO_SYS0 = 16,
DOM_NUM_PERI_AO_SYS1 = 8,
DOM_NUM_PERI_AO_SYS2 = 4,
DOM_NUM_PERI_AO2_SYS0 = 16,
DOM_NUM_PERI_PAR_AO_SYS0 = 16,
};
enum DEVAPC_CFG_INDEX {
DEVAPC_DEBUGSYS_INDEX = 57,
};
struct APC_INFRA_PERI_DOM_16 {
unsigned char d0_permission;
unsigned char d1_permission;
unsigned char d2_permission;
unsigned char d3_permission;
unsigned char d4_permission;
unsigned char d5_permission;
unsigned char d6_permission;
unsigned char d7_permission;
unsigned char d8_permission;
unsigned char d9_permission;
unsigned char d10_permission;
unsigned char d11_permission;
unsigned char d12_permission;
unsigned char d13_permission;
unsigned char d14_permission;
unsigned char d15_permission;
};
struct APC_INFRA_PERI_DOM_8 {
unsigned char d0_permission;
unsigned char d1_permission;
unsigned char d2_permission;
unsigned char d3_permission;
unsigned char d4_permission;
unsigned char d5_permission;
unsigned char d6_permission;
unsigned char d7_permission;
};
struct APC_INFRA_PERI_DOM_4 {
unsigned char d0_permission;
unsigned char d1_permission;
unsigned char d2_permission;
unsigned char d3_permission;
};
#define DAPC_INFRA_AO_SYS0_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
PERM_ATTR6, PERM_ATTR7, PERM_ATTR8, PERM_ATTR9, \
PERM_ATTR10, PERM_ATTR11, PERM_ATTR12, PERM_ATTR13, \
PERM_ATTR14, PERM_ATTR15) \
{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7, \
(unsigned char)PERM_ATTR8, (unsigned char)PERM_ATTR9, \
(unsigned char)PERM_ATTR10, (unsigned char)PERM_ATTR11, \
(unsigned char)PERM_ATTR12, (unsigned char)PERM_ATTR13, \
(unsigned char)PERM_ATTR14, (unsigned char)PERM_ATTR15}
#define DAPC_INFRA_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
PERM_ATTR2, PERM_ATTR3) \
{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3}
#define DAPC_PERI_AO_SYS1_ATTR(DEV_NAME, PERM_ATTR0, PERM_ATTR1, \
PERM_ATTR2, PERM_ATTR3, PERM_ATTR4, PERM_ATTR5, \
PERM_ATTR6, PERM_ATTR7) \
{(unsigned char)PERM_ATTR0, (unsigned char)PERM_ATTR1, \
(unsigned char)PERM_ATTR2, (unsigned char)PERM_ATTR3, \
(unsigned char)PERM_ATTR4, (unsigned char)PERM_ATTR5, \
(unsigned char)PERM_ATTR6, (unsigned char)PERM_ATTR7}
#define DAPC_INFRA_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
#define DAPC_PERI_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
#define DAPC_PERI_AO_SYS2_ATTR(...) DAPC_INFRA_AO_SYS1_ATTR(__VA_ARGS__)
#define DAPC_PERI_AO2_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
#define DAPC_PERI_PAR_AO_SYS0_ATTR(...) DAPC_INFRA_AO_SYS0_ATTR(__VA_ARGS__)
/******************************************************************************
* UTILITY DEFINITION
******************************************************************************/
#define devapc_writel(VAL, REG) mmio_write_32((uintptr_t)REG, VAL)
#define devapc_readl(REG) mmio_read_32((uintptr_t)REG)
/******************************************************************************/
/* Device APC AO for INFRA AO */
#define DEVAPC_INFRA_AO_SYS0_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x0000)
#define DEVAPC_INFRA_AO_SYS1_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x1000)
#define DEVAPC_INFRA_AO_SYS2_D0_APC_0 (DEVAPC_INFRA_AO_BASE + 0x2000)
#define DEVAPC_INFRA_AO_MAS_SEC_0 (DEVAPC_INFRA_AO_BASE + 0x0A00)
/******************************************************************************/
/* Device APC AO for PERI AO */
#define DEVAPC_PERI_AO_SYS0_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x0000)
#define DEVAPC_PERI_AO_SYS1_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x1000)
#define DEVAPC_PERI_AO_SYS2_D0_APC_0 (DEVAPC_PERI_AO_BASE + 0x2000)
#define DEVAPC_PERI_AO_MAS_SEC_0 (DEVAPC_PERI_AO_BASE + 0x0A00)
/******************************************************************************/
/* Device APC AO for PERI AO2 */
#define DEVAPC_PERI_AO2_SYS0_D0_APC_0 (DEVAPC_PERI_AO2_BASE + 0x0000)
/******************************************************************************/
/* Device APC AO for PERI PAR AO */
#define DEVAPC_PERI_PAR_AO_SYS0_D0_APC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0000)
#define DEVAPC_PERI_PAR_AO_MAS_SEC_0 (DEVAPC_PERI_PAR_AO_BASE + 0x0A00)
/******************************************************************************/
/******************************************************************************
* Variable DEFINITION
******************************************************************************/
#define MOD_NO_IN_1_DEVAPC 16
#endif /* DEVAPC_H */

44
plat/mediatek/mt8192/include/platform_def.h
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@ -26,26 +26,30 @@
#define MTK_MCDI_SRAM_BASE 0x11B000
#define MTK_MCDI_SRAM_MAP_SIZE 0x1000
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define DVFSRC_BASE (IO_PHYS + 0x00012000)
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
#define EMI_BASE (IO_PHYS + 0x00219000)
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
#define MMSYS_BASE (IO_PHYS + 0x04000000)
#define TOPCKGEN_BASE (IO_PHYS + 0x00000000)
#define INFRACFG_AO_BASE (IO_PHYS + 0x00001000)
#define GPIO_BASE (IO_PHYS + 0x00005000)
#define SPM_BASE (IO_PHYS + 0x00006000)
#define APMIXEDSYS (IO_PHYS + 0x0000C000)
#define DVFSRC_BASE (IO_PHYS + 0x00012000)
#define PMIC_WRAP_BASE (IO_PHYS + 0x00026000)
#define DEVAPC_INFRA_AO_BASE (IO_PHYS + 0x00030000)
#define DEVAPC_PERI_AO_BASE (IO_PHYS + 0x00034000)
#define DEVAPC_PERI_AO2_BASE (IO_PHYS + 0x00038000)
#define DEVAPC_PERI_PAR_AO_BASE (IO_PHYS + 0x0003C000)
#define EMI_BASE (IO_PHYS + 0x00219000)
#define EMI_MPU_BASE (IO_PHYS + 0x00226000)
#define SSPM_MBOX_BASE (IO_PHYS + 0x00480000)
#define IOCFG_RM_BASE (IO_PHYS + 0x01C20000)
#define IOCFG_BM_BASE (IO_PHYS + 0x01D10000)
#define IOCFG_BL_BASE (IO_PHYS + 0x01D30000)
#define IOCFG_BR_BASE (IO_PHYS + 0x01D40000)
#define IOCFG_LM_BASE (IO_PHYS + 0x01E20000)
#define IOCFG_LB_BASE (IO_PHYS + 0x01E70000)
#define IOCFG_RT_BASE (IO_PHYS + 0x01EA0000)
#define IOCFG_LT_BASE (IO_PHYS + 0x01F20000)
#define IOCFG_TL_BASE (IO_PHYS + 0x01F30000)
#define MMSYS_BASE (IO_PHYS + 0x04000000)
/*******************************************************************************
* UART related constants
******************************************************************************/

2
plat/mediatek/mt8192/platform.mk
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@ -13,6 +13,7 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/include/ \
-I${MTK_PLAT_SOC}/drivers/ \
-I${MTK_PLAT_SOC}/drivers/dcm \
-I${MTK_PLAT_SOC}/drivers/devapc \
-I${MTK_PLAT_SOC}/drivers/emi_mpu/ \
-I${MTK_PLAT_SOC}/drivers/gpio/ \
-I${MTK_PLAT_SOC}/drivers/mcdi/ \
@ -59,6 +60,7 @@ BL31_SOURCES += common/desc_image_load.c \
${MTK_PLAT_SOC}/plat_sip_calls.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm.c \
${MTK_PLAT_SOC}/drivers/dcm/mtk_dcm_utils.c \
${MTK_PLAT_SOC}/drivers/devapc/devapc.c \
${MTK_PLAT_SOC}/drivers/emi_mpu/emi_mpu.c \
${MTK_PLAT_SOC}/drivers/gpio/mtgpio.c \
${MTK_PLAT_SOC}/drivers/mcdi/mt_cpu_pm.c \