From a2aedac221d36624ee1da27741b7f2a0daaa6345 Mon Sep 17 00:00:00 2001 From: Antonio Nino Diaz Date: Wed, 15 Nov 2017 11:45:35 +0000 Subject: [PATCH] Replace magic numbers in linkerscripts by PAGE_SIZE When defining different sections in linker scripts it is needed to align them to multiples of the page size. In most linker scripts this is done by aligning to the hardcoded value 4096 instead of PAGE_SIZE. This may be confusing when taking a look at all the codebase, as 4096 is used in some parts that aren't meant to be a multiple of the page size. Change-Id: I36c6f461c7782437a58d13d37ec8b822a1663ec1 Signed-off-by: Antonio Nino Diaz --- bl1/bl1.ld.S | 11 ++++++----- bl2/bl2.ld.S | 13 +++++++------ bl2u/bl2u.ld.S | 13 +++++++------ bl31/bl31.ld.S | 19 ++++++++++--------- bl32/sp_min/sp_min.ld.S | 13 +++++++------ bl32/tsp/tsp.ld.S | 13 +++++++------ include/plat/arm/common/arm_common.ld.S | 8 +++++--- plat/mediatek/mt6795/bl31.ld.S | 9 +++++---- plat/rockchip/rk3399/include/plat.ld.S | 20 +++++++++++--------- 9 files changed, 65 insertions(+), 54 deletions(-) diff --git a/bl1/bl1.ld.S b/bl1/bl1.ld.S index 2c453bd2c..e4c454b31 100644 --- a/bl1/bl1.ld.S +++ b/bl1/bl1.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -18,7 +19,7 @@ MEMORY { SECTIONS { . = BL1_RO_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL1_RO_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -27,7 +28,7 @@ SECTIONS *bl1_entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >ROM @@ -88,7 +89,7 @@ SECTIONS "cpu_ops not defined for this platform.") . = BL1_RW_BASE; - ASSERT(BL1_RW_BASE == ALIGN(4096), + ASSERT(BL1_RW_BASE == ALIGN(PAGE_SIZE), "BL1_RW_BASE address is not aligned on a page boundary.") /* @@ -141,7 +142,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; @@ -150,7 +151,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM #endif diff --git a/bl2/bl2.ld.S b/bl2/bl2.ld.S index f3ab70614..4fe78f9e9 100644 --- a/bl2/bl2.ld.S +++ b/bl2/bl2.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -18,7 +19,7 @@ MEMORY { SECTIONS { . = BL2_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL2_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -27,7 +28,7 @@ SECTIONS *bl2_entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >RAM @@ -41,7 +42,7 @@ SECTIONS KEEP(*(.img_parser_lib_descs)) __PARSER_LIB_DESCS_END__ = .; - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RODATA_END__ = .; } >RAM #else @@ -64,7 +65,7 @@ SECTIONS * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM #endif @@ -120,7 +121,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; @@ -129,7 +130,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM #endif diff --git a/bl2u/bl2u.ld.S b/bl2u/bl2u.ld.S index efae293dd..da587172e 100644 --- a/bl2u/bl2u.ld.S +++ b/bl2u/bl2u.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -18,7 +19,7 @@ MEMORY { SECTIONS { . = BL2U_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL2U_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -27,14 +28,14 @@ SECTIONS *bl2u_entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >RAM .rodata . : { __RODATA_START__ = .; *(.rodata*) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RODATA_END__ = .; } >RAM #else @@ -51,7 +52,7 @@ SECTIONS * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM #endif @@ -107,7 +108,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; @@ -116,7 +117,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM #endif diff --git a/bl31/bl31.ld.S b/bl31/bl31.ld.S index 7f442d008..dd046c431 100644 --- a/bl31/bl31.ld.S +++ b/bl31/bl31.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -22,7 +23,7 @@ MEMORY { SECTIONS { . = BL31_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -31,7 +32,7 @@ SECTIONS *bl31_entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >RAM @@ -66,7 +67,7 @@ SECTIONS . = ALIGN(8); #include - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RODATA_END__ = .; } >RAM #else @@ -110,7 +111,7 @@ SECTIONS * executable. No RW data from the next section must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM #endif @@ -127,10 +128,10 @@ SECTIONS * There's no need to include this into the RO section of BL31 because it * doesn't need to be accessed by BL31. */ - spm_shim_exceptions : ALIGN(4096) { + spm_shim_exceptions : ALIGN(PAGE_SIZE) { __SPM_SHIM_EXCEPTIONS_START__ = .; *(.spm_shim_exceptions) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __SPM_SHIM_EXCEPTIONS_END__ = .; } >RAM #endif @@ -223,7 +224,7 @@ SECTIONS __SP_IMAGE_XLAT_TABLES_START__ = .; *secure_partition*.o(xlat_table) /* Make sure that the rest of the page is empty. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __SP_IMAGE_XLAT_TABLES_END__ = .; #endif *(xlat_table) @@ -236,7 +237,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; /* * Bakery locks are stored in coherent memory @@ -251,7 +252,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM #endif diff --git a/bl32/sp_min/sp_min.ld.S b/bl32/sp_min/sp_min.ld.S index fc44d5248..8202cf9e3 100644 --- a/bl32/sp_min/sp_min.ld.S +++ b/bl32/sp_min/sp_min.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(elf32-littlearm) OUTPUT_ARCH(arm) @@ -18,7 +19,7 @@ MEMORY { SECTIONS { . = BL32_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL32_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -27,7 +28,7 @@ SECTIONS *entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >RAM @@ -54,7 +55,7 @@ SECTIONS . = ALIGN(8); #include - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RODATA_END__ = .; } >RAM #else @@ -91,7 +92,7 @@ SECTIONS * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory block is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM #endif @@ -186,7 +187,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; /* * Bakery locks are stored in coherent memory @@ -201,7 +202,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM diff --git a/bl32/tsp/tsp.ld.S b/bl32/tsp/tsp.ld.S index 2b672efee..d256b46c8 100644 --- a/bl32/tsp/tsp.ld.S +++ b/bl32/tsp/tsp.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -19,7 +20,7 @@ MEMORY { SECTIONS { . = BL32_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL32_BASE address is not aligned on a page boundary.") #if SEPARATE_CODE_AND_RODATA @@ -28,14 +29,14 @@ SECTIONS *tsp_entrypoint.o(.text*) *(.text*) *(.vectors) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __TEXT_END__ = .; } >RAM .rodata . : { __RODATA_START__ = .; *(.rodata*) - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RODATA_END__ = .; } >RAM #else @@ -51,7 +52,7 @@ SECTIONS * read-only, executable. No RW data from the next section must * creep in. Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM #endif @@ -106,7 +107,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; *(tzfw_coherent_mem) __COHERENT_RAM_END_UNALIGNED__ = .; @@ -115,7 +116,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM #endif diff --git a/include/plat/arm/common/arm_common.ld.S b/include/plat/arm/common/arm_common.ld.S index 478b08c2a..6edfa099d 100644 --- a/include/plat/arm/common/arm_common.ld.S +++ b/include/plat/arm/common/arm_common.ld.S @@ -6,6 +6,8 @@ #ifndef __ARM_COMMON_LD_S__ #define __ARM_COMMON_LD_S__ +#include + MEMORY { EL3_SEC_DRAM (rw): ORIGIN = ARM_EL3_TZC_DRAM1_BASE, LENGTH = ARM_EL3_TZC_DRAM1_SIZE } @@ -13,14 +15,14 @@ MEMORY { SECTIONS { . = ARM_EL3_TZC_DRAM1_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "ARM_EL3_TZC_DRAM_BASE address is not aligned on a page boundary.") - el3_tzc_dram (NOLOAD) : ALIGN(4096) { + el3_tzc_dram (NOLOAD) : ALIGN(PAGE_SIZE) { __EL3_SEC_DRAM_START__ = .; *(arm_el3_tzc_dram) __EL3_SEC_DRAM_UNALIGNED_END__ = .; - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __EL3_SEC_DRAM_END__ = .; } >EL3_SEC_DRAM } diff --git a/plat/mediatek/mt6795/bl31.ld.S b/plat/mediatek/mt6795/bl31.ld.S index 0f60a0c69..eacb1b27f 100644 --- a/plat/mediatek/mt6795/bl31.ld.S +++ b/plat/mediatek/mt6795/bl31.ld.S @@ -5,6 +5,7 @@ */ #include +#include OUTPUT_FORMAT(PLATFORM_LINKER_FORMAT) OUTPUT_ARCH(PLATFORM_LINKER_ARCH) @@ -29,7 +30,7 @@ SECTIONS *(.vectors) } >RAM - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "BL31_BASE address is not aligned on a page boundary.") ro . : { @@ -58,7 +59,7 @@ SECTIONS * executable. No RW data from the next section must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __RO_END__ = .; } >RAM @@ -144,7 +145,7 @@ SECTIONS * are not mixed with normal data. This is required to set up the correct * memory attributes for the coherent data page tables. */ - coherent_ram (NOLOAD) : ALIGN(4096) { + coherent_ram (NOLOAD) : ALIGN(PAGE_SIZE) { __COHERENT_RAM_START__ = .; /* * Bakery locks are stored in coherent memory @@ -159,7 +160,7 @@ SECTIONS * as device memory. No other unexpected data must creep in. * Ensure the rest of the current memory page is unused. */ - . = NEXT(4096); + . = NEXT(PAGE_SIZE); __COHERENT_RAM_END__ = .; } >RAM2 #endif diff --git a/plat/rockchip/rk3399/include/plat.ld.S b/plat/rockchip/rk3399/include/plat.ld.S index c42d9a9aa..85f4dc334 100644 --- a/plat/rockchip/rk3399/include/plat.ld.S +++ b/plat/rockchip/rk3399/include/plat.ld.S @@ -6,6 +6,8 @@ #ifndef __ROCKCHIP_PLAT_LD_S__ #define __ROCKCHIP_PLAT_LD_S__ +#include + MEMORY { SRAM (rwx): ORIGIN = SRAM_BASE, LENGTH = SRAM_SIZE PMUSRAM (rwx): ORIGIN = PMUSRAM_BASE, LENGTH = PMUSRAM_RSIZE @@ -14,7 +16,7 @@ MEMORY { SECTIONS { . = SRAM_BASE; - ASSERT(. == ALIGN(4096), + ASSERT(. == ALIGN(PAGE_SIZE), "SRAM_BASE address is not aligned on a page boundary.") /* @@ -27,40 +29,40 @@ SECTIONS * | sram data * ---------------- */ - .incbin_sram : ALIGN(4096) { + .incbin_sram : ALIGN(PAGE_SIZE) { __sram_incbin_start = .; *(.sram.incbin) __sram_incbin_real_end = .; - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __sram_incbin_end = .; } >SRAM ASSERT((__sram_incbin_real_end - __sram_incbin_start) <= SRAM_BIN_LIMIT, ".incbin_sram has exceeded its limit") - .text_sram : ALIGN(4096) { + .text_sram : ALIGN(PAGE_SIZE) { __bl31_sram_text_start = .; *(.sram.text) *(.sram.rodata) __bl31_sram_text_real_end = .; - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __bl31_sram_text_end = .; } >SRAM ASSERT((__bl31_sram_text_real_end - __bl31_sram_text_start) <= SRAM_TEXT_LIMIT, ".text_sram has exceeded its limit") - .data_sram : ALIGN(4096) { + .data_sram : ALIGN(PAGE_SIZE) { __bl31_sram_data_start = .; *(.sram.data) __bl31_sram_data_real_end = .; - . = ALIGN(4096); + . = ALIGN(PAGE_SIZE); __bl31_sram_data_end = .; } >SRAM ASSERT((__bl31_sram_data_real_end - __bl31_sram_data_start) <= SRAM_DATA_LIMIT, ".data_sram has exceeded its limit") - .stack_sram : ALIGN(4096) { + .stack_sram : ALIGN(PAGE_SIZE) { __bl31_sram_stack_start = .; - . += 4096; + . += PAGE_SIZE; __bl31_sram_stack_end = .; } >SRAM