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Make the memory layout more flexible 

Currently the platform code gets to define the base address of each
boot loader image. However, the linker scripts couteract this
flexibility by enforcing a fixed overall layout of the different
images. For example, they require that the BL3-1 image sits below
the BL2 image. Choosing BL3-1 and BL2 base addresses in such a way
that it violates this constraint makes the build fail at link-time.

This patch requires the platform code to now define a limit address
for each image. The linker scripts check that the image fits within
these bounds so they don't rely anymore on the position of a given
image in regard to the others.

Fixes ARM-software/tf-issues#163

Change-Id: I8c108646825da19a6a8dfb091b613e1dd4ae133c
This commit is contained in:
Sandrine Bailleux 2014-05-22 15:28:26 +01:00
parent 4f59d8359f
commit a37255a205
5 changed files with 20 additions and 4 deletions
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8
bl1/bl1.ld.S
View File

@ -118,11 +118,17 @@ SECTIONS
__DATA_ROM_START__ = LOADADDR(.data);
__DATA_SIZE__ = SIZEOF(.data);
/*
* The .data section is the last PROGBITS section so its end marks the end
* of the read-only part of BL1's binary.
*/
ASSERT(__DATA_ROM_START__ + __DATA_SIZE__ <= BL1_RO_LIMIT,
"BL1's RO section has exceeded its limit.")
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
ASSERT(. <= BL31_BASE, "BL1 image overlaps BL31 image.")
ASSERT(. <= BL1_RW_LIMIT, "BL1's RW section has exceeded its limit.")
}

2
bl2/bl2.ld.S
View File

@ -117,4 +117,6 @@ SECTIONS
__BSS_SIZE__ = SIZEOF(.bss);
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
ASSERT(. <= BL2_LIMIT, "BL2 image has exceeded its limit.")
}

2
bl31/bl31.ld.S
View File

@ -126,5 +126,5 @@ SECTIONS
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
ASSERT(. <= BL2_BASE, "BL31 image overlaps BL2 image.")
ASSERT(. <= BL31_LIMIT, "BL3-1 image has exceeded its limit.")
}

2
bl32/tsp/tsp.ld.S
View File

@ -119,5 +119,5 @@ SECTIONS
__COHERENT_RAM_UNALIGNED_SIZE__ =
__COHERENT_RAM_END_UNALIGNED__ - __COHERENT_RAM_START__;
ASSERT(. <= BL32_LIMIT, "BL3-2 image does not fit.")
ASSERT(. <= BL32_LIMIT, "BL3-2 image has exceeded its limit.")
}

10
plat/fvp/platform.h
View File

@ -237,21 +237,29 @@
/*******************************************************************************
* BL1 specific defines.
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 base
* BL1 RW data is relocated from ROM to RAM at runtime so we need 2 sets of
* addresses.
******************************************************************************/
#define BL1_RO_BASE TZROM_BASE
#define BL1_RO_LIMIT (TZROM_BASE + TZROM_SIZE)
#define BL1_RW_BASE TZRAM_BASE
#define BL1_RW_LIMIT BL31_BASE
/*******************************************************************************
* BL2 specific defines.
******************************************************************************/
#define BL2_BASE (TZRAM_BASE + TZRAM_SIZE - 0xc000)
#define BL2_LIMIT (TZRAM_BASE + TZRAM_SIZE)
/*******************************************************************************
* BL31 specific defines.
******************************************************************************/
#define BL31_BASE (TZRAM_BASE + 0x6000)
#if TSP_RAM_LOCATION_ID == TSP_IN_TZRAM
#define BL31_LIMIT BL32_BASE
#elif TSP_RAM_LOCATION_ID == TSP_IN_TZDRAM
#define BL31_LIMIT BL2_BASE
#endif
/*******************************************************************************
* BL32 specific defines.