From 9eb1bb63e1d51dd85402227f7d904ae004ef49d9 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Mon, 9 Dec 2019 09:53:28 +0800 Subject: [PATCH 1/2] plat: imx8m: Keep A53 PLAT on in wait mode(ret) Keep A53 PLAT(SCU) power domain on in wait mode(ret). RBC count only need to be set in PLAT OFF mode, so change it accordingly. Signed-off-by: Jacky Bai Change-Id: Ie55e25c8210d298506fc4dca7a9653583db45e0c --- plat/imx/imx8m/gpc_common.c | 8 +++----- plat/imx/imx8m/imx8m_psci_common.c | 2 +- 2 files changed, 4 insertions(+), 6 deletions(-) diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index eb2801cea..8aae1a62b 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -133,14 +133,12 @@ void imx_set_cluster_powerdown(unsigned int last_core, uint8_t power_state) val = mmio_read_32(IMX_GPC_BASE + LPCR_A53_AD); val &= ~EN_L2_WFI_PDN; /* L2 cache memory is on in WAIT mode */ - if (is_local_state_off(power_state)) + if (is_local_state_off(power_state)) { val |= (L2PGE | EN_PLAT_PDN); - else - val |= EN_PLAT_PDN; + imx_a53_plat_slot_config(true); + } mmio_write_32(IMX_GPC_BASE + LPCR_A53_AD, val); - - imx_a53_plat_slot_config(true); } else { /* clear the slot and ack for cluster power down */ imx_a53_plat_slot_config(false); diff --git a/plat/imx/imx8m/imx8m_psci_common.c b/plat/imx/imx8m/imx8m_psci_common.c index d6416288e..dbb772dc1 100644 --- a/plat/imx/imx8m/imx8m_psci_common.c +++ b/plat/imx/imx8m/imx8m_psci_common.c @@ -192,7 +192,7 @@ void __dead2 imx_pwr_domain_pwr_down_wfi(const psci_power_state_t *target_state) * drived by the 32K OSC, so delay 30us to make sure the counter * is really running. */ - if (!is_local_state_run(CLUSTER_PWR_STATE(target_state))) { + if (is_local_state_off(CLUSTER_PWR_STATE(target_state))) { imx_set_rbc_count(); udelay(30); } From fb9212be174810096b88d8b8e8686bac17f9c401 Mon Sep 17 00:00:00 2001 From: Jacky Bai Date: Wed, 22 Jul 2020 16:00:50 +0800 Subject: [PATCH 2/2] plat: imx8m: Correct the imr mask reg offset The number of gpc imr mask reg & the offset is different on some SOC, so correct it & replace the magic number with macro define. Signed-off-by: Jacky Bai Change-Id: Ic701675cdd92e043dcd7f06722f2e871068aec74 --- plat/imx/imx8m/gpc_common.c | 2 +- plat/imx/imx8m/imx8mm/include/gpc_reg.h | 2 ++ plat/imx/imx8m/imx8mn/include/gpc_reg.h | 2 ++ plat/imx/imx8m/imx8mp/include/gpc_reg.h | 2 ++ plat/imx/imx8m/imx8mq/include/gpc_reg.h | 2 ++ plat/imx/imx8m/include/gpc.h | 1 - 6 files changed, 9 insertions(+), 2 deletions(-) diff --git a/plat/imx/imx8m/gpc_common.c b/plat/imx/imx8m/gpc_common.c index 8aae1a62b..babcecff0 100644 --- a/plat/imx/imx8m/gpc_common.c +++ b/plat/imx/imx8m/gpc_common.c @@ -16,7 +16,7 @@ #include #include -static uint32_t gpc_imr_offset[] = { 0x30, 0x40, 0x1c0, 0x1d0, }; +static uint32_t gpc_imr_offset[] = { IMR1_CORE0_A53, IMR1_CORE1_A53, IMR1_CORE2_A53, IMR1_CORE3_A53, }; #pragma weak imx_set_cpu_pwr_off #pragma weak imx_set_cpu_pwr_on diff --git a/plat/imx/imx8m/imx8mm/include/gpc_reg.h b/plat/imx/imx8m/imx8mm/include/gpc_reg.h index c697af29b..1a4eae546 100644 --- a/plat/imx/imx8m/imx8mm/include/gpc_reg.h +++ b/plat/imx/imx8m/imx8mm/include/gpc_reg.h @@ -124,4 +124,6 @@ #define VPU_G2_PGC 0xf00 #define VPU_H1_PGC 0xf40 +#define IRQ_IMR_NUM U(4) + #endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/imx8mn/include/gpc_reg.h b/plat/imx/imx8m/imx8mn/include/gpc_reg.h index fd10438a4..8a8136814 100644 --- a/plat/imx/imx8m/imx8mn/include/gpc_reg.h +++ b/plat/imx/imx8m/imx8mn/include/gpc_reg.h @@ -106,4 +106,6 @@ #define GPUMIX_PGC 0xdc0 #define DISPMIX_PGC 0xe80 +#define IRQ_IMR_NUM U(4) + #endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/imx8mp/include/gpc_reg.h b/plat/imx/imx8m/imx8mp/include/gpc_reg.h index 12da6ac7e..7909937b2 100644 --- a/plat/imx/imx8m/imx8mp/include/gpc_reg.h +++ b/plat/imx/imx8m/imx8mp/include/gpc_reg.h @@ -146,4 +146,6 @@ #define MEDIAMIX_ISPDWP_PGC 0xf80 #define DDRMIX_PGC 0xfc0 +#define IRQ_IMR_NUM U(5) + #endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/imx8mq/include/gpc_reg.h b/plat/imx/imx8m/imx8mq/include/gpc_reg.h index 9f472d609..f171bd9d0 100644 --- a/plat/imx/imx8m/imx8mq/include/gpc_reg.h +++ b/plat/imx/imx8m/imx8mq/include/gpc_reg.h @@ -84,4 +84,6 @@ #define MASTER1_MAPPING BIT(1) #define MASTER2_MAPPING BIT(2) +#define IRQ_IMR_NUM U(4) + #endif /* GPC_REG_H */ diff --git a/plat/imx/imx8m/include/gpc.h b/plat/imx/imx8m/include/gpc.h index 89a0b9d39..6f86e1d6b 100644 --- a/plat/imx/imx8m/include/gpc.h +++ b/plat/imx/imx8m/include/gpc.h @@ -25,7 +25,6 @@ #define SLTx_CFG(n) ((SLT0_CFG + ((n) * 4))) #define SLT_COREx_PUP(core_id) (0x2 << ((core_id) * 2)) -#define IRQ_IMR_NUM 4 #define IMR_MASK_ALL 0xffffffff #define IMX_PD_DOMAIN(name, on) \