andrius
/
arm-trusted-firmware
1
0
Fork 0
Code Issues Pull Requests Releases Wiki Activity

plat: tc0: Add TZC DRAM1 region for SPMC and trusted OS 

- Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for TC0_TZC_DRAM1
- Add TC0_NS_DRAM1 base and mapping
- Reserve memory region in tc0.dts

Change-Id: If2431f7f68e4255e28c86a0e89637dab7c424a13
Signed-off-by: Arunachalam Ganapathy <arunachalam.ganapathy@arm.com>
This commit is contained in:
Arunachalam Ganapathy 2020-09-22 12:47:33 +01:00 committed by Manish Pandey
parent d32113c7f3
commit a3ecbb3553
3 changed files with 37 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
fdts/tc0.dts
View File

@ -106,7 +106,7 @@
memory@80000000 {
device_type = "memory";
reg = <0x0 0x80000000 0x0 0x80000000>;
reg = <0x0 0x80000000 0x0 0x7d000000>;
};
psci {

35
plat/arm/board/tc0/include/platform_def.h
View File

@ -21,6 +21,41 @@
#define PLAT_ARM_TRUSTED_SRAM_SIZE 0x00080000 /* 512 KB */
/*
* The top 16MB of ARM_DRAM1 is configured as secure access only using the TZC,
* its base is ARM_AP_TZC_DRAM1_BASE.
*
* Reserve 32MB below ARM_AP_TZC_DRAM1_BASE for:
* - BL32_BASE when SPD_spmd is enabled
* - Region to load Trusted OS
*/
#define TC0_TZC_DRAM1_BASE (ARM_AP_TZC_DRAM1_BASE - \
TC0_TZC_DRAM1_SIZE)
#define TC0_TZC_DRAM1_SIZE UL(0x02000000) /* 32 MB */
#define TC0_TZC_DRAM1_END (TC0_TZC_DRAM1_BASE + \
TC0_TZC_DRAM1_SIZE - 1)
#define TC0_NS_DRAM1_BASE ARM_DRAM1_BASE
#define TC0_NS_DRAM1_SIZE (ARM_DRAM1_SIZE - \
ARM_TZC_DRAM1_SIZE - \
TC0_TZC_DRAM1_SIZE)
#define TC0_NS_DRAM1_END (TC0_NS_DRAM1_BASE + \
TC0_NS_DRAM1_SIZE - 1)
/*
* Mappings for TC0 DRAM1 (non-secure) and TC0 TZC DRAM1 (secure)
*/
#define TC0_MAP_NS_DRAM1 MAP_REGION_FLAT( \
TC0_NS_DRAM1_BASE, \
TC0_NS_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_NS)
#define TC0_MAP_TZC_DRAM1 MAP_REGION_FLAT( \
TC0_TZC_DRAM1_BASE, \
TC0_TZC_DRAM1_SIZE, \
MT_MEMORY | MT_RW | MT_SECURE)
/*
* PLAT_ARM_MMAP_ENTRIES depends on the number of entries in the
* plat_arm_mmap array defined for each BL stage.

2
plat/arm/board/tc0/tc0_plat.c
View File

@ -38,7 +38,7 @@ const mmap_region_t plat_arm_mmap[] = {
ARM_MAP_SHARED_RAM,
TC0_FLASH0_RO,
TC0_MAP_DEVICE,
ARM_MAP_NS_DRAM1,
TC0_MAP_NS_DRAM1,
#if ARM_BL31_IN_DRAM
ARM_MAP_BL31_SEC_DRAM,
#endif