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Merge pull request #1804 from antonio-nino-diaz-arm/an/cleanup 

Minor cleanup
This commit is contained in:
Antonio Niño Díaz 2019-02-05 11:31:15 +00:00 committed by GitHub
parent 49dd04815f 5e447816c7
commit a45ccf135e
No known key found for this signature in database
GPG Key ID: 4AEE18F83AFDEB23
36 changed files with 66 additions and 260 deletions
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2
bl32/tsp/tsp_main.c
View File

@ -38,7 +38,7 @@ work_statistics_t tsp_stats[PLATFORM_CORE_COUNT];
* linker symbol __BL32_END__. Use these addresses to compute the TSP image
* size.
******************************************************************************/
#define BL32_TOTAL_LIMIT (unsigned long)(&__BL32_END__)
#define BL32_TOTAL_LIMIT BL32_END
#define BL32_TOTAL_SIZE (BL32_TOTAL_LIMIT - (unsigned long) BL32_BASE)
static tsp_args_t *set_smc_args(uint64_t arg0,

11
docs/porting-guide.rst
View File

@ -103,20 +103,13 @@ File : platform\_def.h [mandatory]
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Each platform must ensure that a header file of this name is in the system
include path with the following constants defined. This may require updating the
list of ``PLAT_INCLUDES`` in the ``platform.mk`` file. In the Arm development
platforms, this file is found in ``plat/arm/board/<plat_name>/include/``.
include path with the following constants defined. This will require updating
the list of ``PLAT_INCLUDES`` in the ``platform.mk`` file.
Platform ports may optionally use the file `include/plat/common/common\_def.h`_,
which provides typical values for some of the constants below. These values are
likely to be suitable for all platform ports.
Platform ports that want to be aligned with standard Arm platforms (for example
FVP and Juno) may also use `include/plat/arm/common/arm\_def.h`_, which provides
standard values for some of the constants below. However, this requires the
platform port to define additional platform porting constants in
``platform_def.h``. These additional constants are not documented here.
- **#define : PLATFORM\_LINKER\_FORMAT**
Defines the linker format used by the platform, for example

41
include/common/bl_common.h
View File

@ -69,40 +69,37 @@
* BL images
*/
#if SEPARATE_CODE_AND_RODATA
IMPORT_SYM(unsigned long, __TEXT_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __TEXT_END__, BL_CODE_END);
IMPORT_SYM(unsigned long, __RODATA_START__, BL_RO_DATA_BASE);
IMPORT_SYM(unsigned long, __RODATA_END__, BL_RO_DATA_END);
IMPORT_SYM(uintptr_t, __TEXT_START__, BL_CODE_BASE);
IMPORT_SYM(uintptr_t, __TEXT_END__, BL_CODE_END);
IMPORT_SYM(uintptr_t, __RODATA_START__, BL_RO_DATA_BASE);
IMPORT_SYM(uintptr_t, __RODATA_END__, BL_RO_DATA_END);
#else
IMPORT_SYM(unsigned long, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(unsigned long, __RO_END__, BL_CODE_END);
IMPORT_SYM(uintptr_t, __RO_START__, BL_CODE_BASE);
IMPORT_SYM(uintptr_t, __RO_END__, BL_CODE_END);
#endif
#if defined(IMAGE_BL1)
IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
IMPORT_SYM(uintptr_t, __BL1_ROM_END__, BL1_ROM_END);
IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
IMPORT_SYM(uintptr_t, __BL1_RAM_START__, BL1_RAM_BASE);
IMPORT_SYM(uintptr_t, __BL1_RAM_END__, BL1_RAM_LIMIT);
#elif defined(IMAGE_BL2)
IMPORT_SYM(unsigned long, __BL2_END__, BL2_END);
IMPORT_SYM(uintptr_t, __BL2_END__, BL2_END);
#elif defined(IMAGE_BL2U)
IMPORT_SYM(unsigned long, __BL2U_END__, BL2U_END);
IMPORT_SYM(uintptr_t, __BL2U_END__, BL2U_END);
#elif defined(IMAGE_BL31)
IMPORT_SYM(unsigned long, __BL31_START__, BL31_START);
IMPORT_SYM(unsigned long, __BL31_END__, BL31_END);
IMPORT_SYM(uintptr_t, __BL31_START__, BL31_START);
IMPORT_SYM(uintptr_t, __BL31_END__, BL31_END);
#elif defined(IMAGE_BL32)
IMPORT_SYM(unsigned long, __BL32_END__, BL32_END);
IMPORT_SYM(uintptr_t, __BL32_END__, BL32_END);
#endif /* IMAGE_BLX */
/* The following symbols are only exported from the BL2 at EL3 linker script. */
#if BL2_IN_XIP_MEM && defined(IMAGE_BL2)
extern uintptr_t __BL2_ROM_END__;
#define BL2_ROM_END (uintptr_t)(&__BL2_ROM_END__)
IMPORT_SYM(uintptr_t, __BL2_ROM_END__, BL2_ROM_END);
extern uintptr_t __BL2_RAM_START__;
extern uintptr_t __BL2_RAM_END__;
#define BL2_RAM_BASE (uintptr_t)(&__BL2_RAM_START__)
#define BL2_RAM_LIMIT (uintptr_t)(&__BL2_RAM_END__)
IMPORT_SYM(uintptr_t, __BL2_RAM_START__, BL2_RAM_BASE);
IMPORT_SYM(uintptr_t, __BL2_RAM_END__, BL2_RAM_END);
#endif /* BL2_IN_XIP_MEM */
/*
@ -113,8 +110,8 @@ extern uintptr_t __BL2_RAM_END__;
* page-aligned addresses.
*/
#if USE_COHERENT_MEM
IMPORT_SYM(unsigned long, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
IMPORT_SYM(unsigned long, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
IMPORT_SYM(uintptr_t, __COHERENT_RAM_START__, BL_COHERENT_RAM_BASE);
IMPORT_SYM(uintptr_t, __COHERENT_RAM_END__, BL_COHERENT_RAM_END);
#endif
/*******************************************************************************

3
lib/xlat_tables_v2/aarch64/enable_mmu.S
View File

@ -86,9 +86,10 @@
.endm
/*
* Define MMU-enabling functions for EL1 and EL3:
* Define MMU-enabling functions for EL1, EL2 and EL3:
*
* enable_mmu_direct_el1
* enable_mmu_direct_el2
* enable_mmu_direct_el3
*/
define_mmu_enable_func 1

2
plat/arm/common/tsp/arm_tsp_setup.c
View File

@ -15,8 +15,6 @@
#include <drivers/console.h>
#include <plat/arm/common/plat_arm.h>
#define BL32_END (unsigned long)(&__BL32_END__)
/* Weak definitions may be overridden in specific ARM standard platform */
#pragma weak tsp_early_platform_setup
#pragma weak tsp_platform_setup

17
plat/arm/css/sgi/sgi_plat.c
View File

@ -15,23 +15,6 @@
#include <plat/common/platform.h>
#include <services/secure_partition.h>
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL1_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL1_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define BL31_COHERENT_RAM_BASE (uintptr_t)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (uintptr_t)(&__COHERENT_RAM_END__)
#endif
#define SGI_MAP_FLASH0_RO MAP_REGION_FLAT(V2M_FLASH0_BASE,\
V2M_FLASH0_SIZE, \
MT_DEVICE | MT_RO | MT_SECURE)

29
plat/hisilicon/hikey/hikey_bl2_setup.c
View File

@ -29,26 +29,7 @@
#include <hisi_sram_map.h>
#include "hikey_private.h"
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL2_RW_BASE (BL2_RO_LIMIT)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define BL2_RW_BASE (BL_CODE_END)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
@ -295,10 +276,10 @@ void bl2_el3_plat_arch_setup(void)
{
hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
bl2_el3_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)

27
plat/hisilicon/hikey/hikey_bl31_setup.c
View File

@ -25,25 +25,6 @@
#include "hikey_private.h"
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
@ -135,10 +116,10 @@ void bl31_plat_arch_setup(void)
{
hikey_init_mmu_el3(BL31_BASE,
BL31_LIMIT - BL31_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
/* Initialize EDMAC controller with non-secure mode. */

3
plat/hisilicon/hikey/platform.mk
View File

@ -45,8 +45,7 @@ endif
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iplat/hisilicon/hikey/include
PLAT_INCLUDES := -Iplat/hisilicon/hikey/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
lib/xlat_tables/aarch64/xlat_tables.c \

29
plat/hisilicon/hikey960/hikey960_bl2_setup.c
View File

@ -28,26 +28,7 @@
#include "hikey960_def.h"
#include "hikey960_private.h"
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL2_RW_BASE (BL2_RO_LIMIT)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define BL2_RW_BASE (BL_CODE_END)
static meminfo_t bl2_el3_tzram_layout;
static console_pl011_t console;
@ -312,10 +293,10 @@ void bl2_el3_plat_arch_setup(void)
{
hikey960_init_mmu_el3(bl2_el3_tzram_layout.total_base,
bl2_el3_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)

27
plat/hisilicon/hikey960/hikey960_bl31_setup.c
View File

@ -27,25 +27,6 @@
#include "hikey960_def.h"
#include "hikey960_private.h"
/*
* The next 2 constants identify the extents of the code & RO data region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __RO_START__ and __RO_END__ linker symbols refer to page-aligned addresses.
*/
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols refer to
* page-aligned addresses.
*/
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static entry_point_info_t bl32_ep_info;
static entry_point_info_t bl33_ep_info;
static console_pl011_t console;
@ -140,10 +121,10 @@ void bl31_plat_arch_setup(void)
{
hikey960_init_mmu_el3(BL31_BASE,
BL31_LIMIT - BL31_BASE,
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
static void hikey960_edma_init(void)

3
plat/hisilicon/hikey960/platform.mk
View File

@ -40,8 +40,7 @@ endif
USE_COHERENT_MEM := 1
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Iplat/hisilicon/hikey960/include
PLAT_INCLUDES := -Iplat/hisilicon/hikey960/include
PLAT_BL_COMMON_SOURCES := drivers/arm/pl011/aarch64/pl011_console.S \
drivers/delay_timer/delay_timer.c \

16
plat/hisilicon/poplar/bl2_plat_setup.c
View File

@ -24,14 +24,6 @@
#include "hi3798cv200.h"
#include "plat_private.h"
/* Memory ranges for code and read only data sections */
#define BL2_RO_BASE (unsigned long)(&__RO_START__)
#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
/* Memory ranges for coherent memory section */
#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
static console_pl011_t console;
@ -206,10 +198,10 @@ void bl2_plat_arch_setup(void)
{
plat_configure_mmu_el1(bl2_tzram_layout.total_base,
bl2_tzram_layout.total_size,
BL2_RO_BASE,
BL2_RO_LIMIT,
BL2_COHERENT_RAM_BASE,
BL2_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
}
void bl2_platform_setup(void)

16
plat/hisilicon/poplar/bl31_plat_setup.c
View File

@ -25,14 +25,6 @@
#include "hi3798cv200.h"
#include "plat_private.h"
/* Memory ranges for code and RO data sections */
#define BL31_RO_BASE (unsigned long)(&__RO_START__)
#define BL31_RO_LIMIT (unsigned long)(&__RO_END__)
/* Memory ranges for coherent memory section */
#define BL31_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL31_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#define TZPC_SEC_ATTR_CTRL_VALUE (0x9DB98D45)
static entry_point_info_t bl32_image_ep_info;
@ -133,10 +125,10 @@ void bl31_plat_arch_setup(void)
{
plat_configure_mmu_el3(BL31_BASE,
(BL31_LIMIT - BL31_BASE),
BL31_RO_BASE,
BL31_RO_LIMIT,
BL31_COHERENT_RAM_BASE,
BL31_COHERENT_RAM_LIMIT);
BL_CODE_BASE,
BL_CODE_END,
BL_COHERENT_RAM_BASE,
BL_COHERENT_RAM_END);
INFO("Boot BL33 from 0x%lx for %lu Bytes\n",
bl33_image_ep_info.pc, bl33_image_ep_info.args.arg2);

3
plat/hisilicon/poplar/platform.mk
View File

@ -53,8 +53,7 @@ PLAT_PL061_MAX_GPIOS := 104
$(eval $(call add_define,PLAT_PL061_MAX_GPIOS))
PLAT_INCLUDES := -Iplat/hisilicon/poplar/include \
-Iplat/hisilicon/poplar \
-Iinclude/common/tbbr
-Iplat/hisilicon/poplar
PLAT_BL_COMMON_SOURCES := \
lib/xlat_tables/aarch64/xlat_tables.c \

1
plat/imx/imx7/warp7/platform.mk
View File

@ -21,7 +21,6 @@ endif
# Platform
PLAT_INCLUDES := -Idrivers/imx/uart \
-Iinclude/common/tbbr \
-Iplat/imx/common/include/ \
-Iplat/imx/imx7/warp7/include \
-Idrivers/imx/timer \

2
plat/layerscape/board/ls1043/platform.mk
View File

@ -23,8 +23,6 @@ LS1043_SECURITY_SOURCES := plat/layerscape/common/ls_tzc380.c \
PLAT_INCLUDES := -Iplat/layerscape/board/ls1043/include \
-Iplat/layerscape/common/include \
-Iinclude/lib
PLAT_BL_COMMON_SOURCES := plat/layerscape/common/aarch64/ls_console.S

2
plat/layerscape/common/ls_common.mk
View File

@ -15,8 +15,6 @@ SEPARATE_CODE_AND_RODATA := 1
COLD_BOOT_SINGLE_CPU := 1
PLAT_INCLUDES += -Iinclude/common/tbbr
PLAT_BL_COMMON_SOURCES += plat/layerscape/common/${ARCH}/ls_helpers.S \
plat/layerscape/common/ls_common.c

3
plat/layerscape/common/tsp/ls_tsp_setup.c
View File

@ -4,6 +4,7 @@
* SPDX-License-Identifier: BSD-3-Clause
*/
#include <common/bl_common.h>
#include <common/debug.h>
#include <common/interrupt_props.h>
#include <drivers/arm/gicv2.h>
@ -12,8 +13,6 @@
#include "plat_ls.h"
#include "soc.h"
#define BL32_END (unsigned long)(&__BL32_END__)
static const interrupt_prop_t g0_interrupt_props[] = {
INTR_PROP_DESC(9, GIC_HIGHEST_SEC_PRIORITY,
GICV2_INTR_GROUP0, GIC_INTR_CFG_LEVEL),

5
plat/marvell/a3700/common/a3700_common.mk
View File

@ -84,14 +84,11 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
plat/common/plat_gicv3.c \
drivers/arm/gic/v3/gic500.c
ATF_INCLUDES := -Iinclude/common/tbbr
PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$(PLAT_COMMON_BASE)/include \
-I$(PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_DRV_BASE) \
-I$/drivers/arm/gic/common/ \
$(ATF_INCLUDES)
-I$/drivers/arm/gic/common/
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a3700_common.c \
$(MARVELL_COMMON_BASE)/marvell_cci.c \

5
plat/marvell/a8k/common/a8k_common.mk
View File

@ -45,12 +45,9 @@ MARVELL_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_helpers.c \
plat/common/plat_gicv2.c
ATF_INCLUDES := -Iinclude/common/tbbr
PLAT_INCLUDES := -I$(PLAT_FAMILY_BASE)/$(PLAT) \
-I$(PLAT_COMMON_BASE)/include \
-I$(PLAT_INCLUDE_BASE)/common \
$(ATF_INCLUDES)
-I$(PLAT_INCLUDE_BASE)/common
PLAT_BL_COMMON_SOURCES := $(PLAT_COMMON_BASE)/aarch64/a8k_common.c \
drivers/ti/uart/aarch64/16550_console.S

9
plat/marvell/a8k/common/ble/ble.mk
View File

@ -17,11 +17,10 @@ BLE_SOURCES += $(BLE_PATH)/ble_main.c \
$(PLAT_MARVELL)/common/plat_delay_timer.c \
$(PLAT_MARVELL)/common/marvell_console.c
PLAT_INCLUDES += -I$(MV_DDR_PATH) \
-I$(CURDIR)/include/ \
-I$(CURDIR)/include/lib \
-I$(CURDIR)/include/lib/libc \
-I$(CURDIR)/include/lib/libc/aarch64 \
PLAT_INCLUDES += -I$(MV_DDR_PATH) \
-I$(CURDIR)/include \
-I$(CURDIR)/include/lib/libc \
-I$(CURDIR)/include/lib/libc/aarch64 \
-I$(CURDIR)/drivers/marvell
BLE_LINKERFILE := $(BLE_PATH)/ble.ld.S

10
plat/marvell/common/marvell_bl31_setup.c
View File

@ -8,6 +8,7 @@
#include <assert.h>
#include <arch.h>
#include <common/bl_common.h>
#include <common/debug.h>
#ifdef USE_CCI
#include <drivers/arm/cci.h>
@ -19,15 +20,6 @@
#include <marvell_plat_priv.h>
#include <plat_marvell.h>
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL31 image. These addresses are used by the MMU setup code and
* therefore they must be page-aligned. It is the responsibility of the linker
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.

3
plat/marvell/common/marvell_common.mk
View File

@ -22,8 +22,7 @@ $(eval $(call add_define,ARO_ENABLE))
LLC_ENABLE := 1
$(eval $(call add_define,LLC_ENABLE))
PLAT_INCLUDES += -I. -Iinclude/common -Iinclude/common/tbbr \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common \
PLAT_INCLUDES += -I$(MARVELL_PLAT_INCLUDE_BASE)/common \
-I$(MARVELL_PLAT_INCLUDE_BASE)/common/aarch64

1
plat/mediatek/mt6795/platform.mk
View File

@ -23,7 +23,6 @@ PLAT_INCLUDES := -I${MTK_PLAT}/common/ \
-I${MTK_PLAT_SOC}/drivers/timer/ \
-I${MTK_PLAT_SOC}/include/ \
-Iinclude/plat/arm/common/ \
-Iinclude/common/tbbr/ \
${OEMS_INCLUDES}
PLAT_BL_COMMON_SOURCES := lib/xlat_tables/aarch64/xlat_tables.c \

6
plat/qemu/platform.mk
View File

@ -30,9 +30,7 @@ $(eval $(call add_define,QEMU_LOAD_BL32))
endif
PLAT_PATH := plat/qemu/
PLAT_INCLUDES := -Iinclude/plat/arm/common/ \
-Iplat/qemu/include \
-Iinclude/common/tbbr
PLAT_INCLUDES := -Iplat/qemu/include
ifeq (${ARM_ARCH_MAJOR},8)
PLAT_INCLUDES += -Iinclude/plat/arm/common/${ARCH}
@ -55,8 +53,6 @@ ifneq (${TRUSTED_BOARD_BOOT},0)
drivers/auth/img_parser_mod.c \
drivers/auth/tbbr/tbbr_cot.c
PLAT_INCLUDES += -Iinclude/bl1/tbbr
BL1_SOURCES += ${AUTH_SOURCES} \
bl1/tbbr/tbbr_img_desc.c \
plat/common/tbbr/plat_tbbr.c \

9
plat/qemu/qemu_bl31_setup.c
View File

@ -15,15 +15,6 @@
#include "qemu_private.h"
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL3-1 image. These addresses are used by the MMU setup code and
* therefore they must be page-aligned. It is the responsibility of the linker
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL31_END (unsigned long)(&__BL31_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL3-1 from BL2.

25
plat/qemu/sp_min/sp_min_setup.c
View File

@ -27,29 +27,6 @@
static entry_point_info_t bl33_image_ep_info;
/*
* The next 3 constants identify the extents of the code, RO data region and the
* limit of the BL3-1 image. These addresses are used by the MMU setup code and
* therefore they must be page-aligned. It is the responsibility of the linker
* script to ensure that __RO_START__, __RO_END__ & __BL31_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL32_RO_BASE (unsigned long)(&__RO_START__)
#define BL32_RO_LIMIT (unsigned long)(&__RO_END__)
#define BL32_END (unsigned long)(&__BL32_END__)
#if USE_COHERENT_MEM
/*
* The next 2 constants identify the extents of the coherent memory region.
* These addresses are used by the MMU setup code and therefore they must be
* page-aligned. It is the responsibility of the linker script to ensure that
* __COHERENT_RAM_START__ and __COHERENT_RAM_END__ linker symbols
* refer to page-aligned addresses.
*/
#define BL32_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
#define BL32_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
#endif
/******************************************************************************
* On a GICv2 system, the Group 1 secure interrupts are treated as Group 0
* interrupts.
@ -146,7 +123,7 @@ void sp_min_early_platform_setup2(u_register_t arg0, u_register_t arg1,
void sp_min_plat_arch_setup(void)
{
qemu_configure_mmu_svc_mon(BL32_RO_BASE, BL32_END - BL32_RO_BASE,
BL32_RO_BASE, BL32_RO_LIMIT,
BL_CODE_BASE, BL_CODE_END,
BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END);
}

3
plat/renesas/rcar/platform.mk
View File

@ -306,8 +306,7 @@ include drivers/staging/renesas/rcar/qos/qos.mk
include drivers/staging/renesas/rcar/pfc/pfc.mk
include lib/libfdt/libfdt.mk
PLAT_INCLUDES := -Iinclude/common/tbbr \
-Idrivers/staging/renesas/rcar/ddr \
PLAT_INCLUDES := -Idrivers/staging/renesas/rcar/ddr \
-Idrivers/staging/renesas/rcar/qos \
-Idrivers/renesas/rcar/iic_dvfs \
-Idrivers/renesas/rcar/board \

1
plat/rockchip/rk3328/platform.mk
View File

@ -10,7 +10,6 @@ RK_PLAT_COMMON := ${RK_PLAT}/common
PLAT_INCLUDES := -Idrivers/arm/gic/common/ \
-Idrivers/arm/gic/v2/ \
-Iinclude/plat/common/ \
-I${RK_PLAT_COMMON}/ \
-I${RK_PLAT_COMMON}/include/ \
-I${RK_PLAT_COMMON}/pmusram \

2
plat/rpi3/rpi3_bl31_setup.c
View File

@ -17,8 +17,6 @@
#include "rpi3_private.h"
#define BL31_END (uintptr_t)(&__BL31_END__)
/*
* Placeholder variables for copying the arguments that have been passed to
* BL31 from BL2.

2
plat/socionext/uniphier/platform.mk
View File

@ -72,8 +72,6 @@ ifeq (${TRUSTED_BOARD_BOOT},1)
include drivers/auth/mbedtls/mbedtls_crypto.mk
include drivers/auth/mbedtls/mbedtls_x509.mk
PLAT_INCLUDES += -Iinclude/common/tbbr
BL2_SOURCES += drivers/auth/auth_mod.c \
drivers/auth/crypto_mod.c \
drivers/auth/img_parser_mod.c \

2
plat/socionext/uniphier/tsp/uniphier_tsp_setup.c
View File

@ -6,11 +6,11 @@
#include <platform_def.h>
#include <common/bl_common.h>
#include <lib/xlat_tables/xlat_mmu_helpers.h>
#include "../uniphier.h"
#define BL32_END (unsigned long)(&__BL32_END__)
#define BL32_SIZE ((BL32_END) - (BL32_BASE))
void tsp_early_platform_setup(void)

1
plat/socionext/uniphier/uniphier_bl2_setup.c
View File

@ -21,7 +21,6 @@
#include "uniphier.h"
#define BL2_END (unsigned long)(&__BL2_END__)
#define BL2_SIZE ((BL2_END) - (BL2_BASE))
static int uniphier_bl2_kick_scp;

2
plat/xilinx/zynqmp/bl31_zynqmp_setup.c
View File

@ -16,8 +16,6 @@
#include <plat_private.h>
#define BL31_END (unsigned long)(&__BL31_END__)
static entry_point_info_t bl32_image_ep_info;
static entry_point_info_t bl33_image_ep_info;

3
plat/xilinx/zynqmp/tsp/tsp_plat_setup.c
View File

@ -12,9 +12,6 @@
#include <plat_private.h>
#include <platform_tsp.h>
#define BL32_END (unsigned long)(&__BL32_END__)
/*******************************************************************************
* Initialize the UART
******************************************************************************/