hikey: migrate to bl2_el3
Since non-TF ROM is used in HiKey platform (Hisilicon Hi6220 SoC), replace BL1 by BL2_EL3 in normal boot mode. When we recovery images in recovery mode, keep to use BL1. Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
This commit is contained in:
Haojian Zhuang
parent
a9b3021e14
commit
a628b1ab2a
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@ -91,6 +91,7 @@ Build Procedure
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cd ${BUILD_PATH}/l-loader
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ln -sf ${EDK2_OUTPUT_DIR}/FV/bl1.bin
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ln -sf ${EDK2_OUTPUT_DIR}/FV/bl2.bin
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ln -sf ${BUILD_PATH}/atf-fastboot/build/hikey/${FASTBOOT_BUILD_OPTION}/bl1.bin fastboot.bin
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make hikey PTABLE_LST=aosp-8g
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@ -142,17 +143,18 @@ Flash images in recovery mode
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$sudo apt-get purge modemmanager
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- Run the command to download l-loader.bin into HiKey.
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- Run the command to download recovery.bin into HiKey.
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.. code:: shell
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$sudo python hisi-idt.py -d /dev/ttyUSB1 --img1 l-loader.bin
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$sudo python hisi-idt.py -d /dev/ttyUSB1 --img1 recovery.bin
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- Update images. All aosp or debian images could be fetched from `link <https://builds.96boards.org/>`__.
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.. code:: shell
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$sudo fastboot flash ptable prm_ptable.img
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$sudo fastboot flash loader l-loader.bin
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$sudo fastboot flash fastboot fip.bin
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$sudo fastboot flash boot boot.img
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$sudo fastboot flash cache cache.img
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@ -64,6 +64,7 @@ static const mmap_region_t hikey_mmap[] = {
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MAP_DDR,
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MAP_DEVICE,
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MAP_TSP_MEM,
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MAP_SRAM,
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{0}
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};
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#endif
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -529,9 +529,6 @@ unsigned int bl1_plat_get_next_image_id(void)
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boot_mode = mmio_read_32(ONCHIPROM_PARAM_BASE);
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switch (boot_mode) {
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case BOOT_NORMAL:
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ret = BL2_IMAGE_ID;
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break;
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case BOOT_USB_DOWNLOAD:
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case BOOT_UART_DOWNLOAD:
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ret = NS_BL1U_IMAGE_ID;
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@ -563,7 +560,7 @@ void bl1_plat_set_ep_info(unsigned int image_id,
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unsigned int data = 0;
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if (image_id == BL2_IMAGE_ID)
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return;
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panic();
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inv_dcache_range(NS_BL1U_BASE, NS_BL1U_SIZE);
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__asm__ volatile ("mrs %0, cpacr_el1" : "=r"(data));
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do {
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2016-2017, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2016-2018, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -28,7 +28,7 @@ static bl_mem_params_node_t bl2_mem_params_descs[] = {
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VERSION_2, entry_point_info_t, SECURE | NON_EXECUTABLE),
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SET_STATIC_PARAM_HEAD(image_info, PARAM_IMAGE_BINARY,
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VERSION_2, image_info_t, 0),
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VERSION_2, image_info_t, IMAGE_ATTRIB_PLAT_SETUP),
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.image_info.image_base = SCP_BL2_BASE,
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.image_info.image_max_size = SCP_BL2_SIZE,
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@ -13,13 +13,17 @@
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#include <dw_mmc.h>
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#include <emmc.h>
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#include <errno.h>
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#include <gpio.h>
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#include <hi6220.h>
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#include <hi6553.h>
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#include <hisi_mcu.h>
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#include <hisi_sram_map.h>
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#include <mmio.h>
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#ifdef SPD_opteed
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#include <optee_utils.h>
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#endif
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#include <pl061_gpio.h>
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#include <platform.h>
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#include <platform_def.h>
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#include <sp804_delay_timer.h>
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#include <string.h>
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@ -36,6 +40,8 @@
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#define BL2_RO_BASE (unsigned long)(&__RO_START__)
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#define BL2_RO_LIMIT (unsigned long)(&__RO_END__)
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#define BL2_RW_BASE (BL2_RO_LIMIT)
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/*
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* The next 2 constants identify the extents of the coherent memory region.
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* These addresses are used by the MMU setup code and therefore they must be
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@ -46,7 +52,13 @@
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#define BL2_COHERENT_RAM_BASE (unsigned long)(&__COHERENT_RAM_START__)
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#define BL2_COHERENT_RAM_LIMIT (unsigned long)(&__COHERENT_RAM_END__)
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static meminfo_t bl2_tzram_layout __aligned(CACHE_WRITEBACK_GRANULE);
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static meminfo_t bl2_el3_tzram_layout;
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enum {
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BOOT_MODE_RECOVERY = 0,
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BOOT_MODE_NORMAL,
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BOOT_MODE_MASK = 1,
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};
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/*******************************************************************************
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* Transfer SCP_BL2 from Trusted RAM using the SCP Download protocol.
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@ -264,29 +276,428 @@ static void hikey_jumper_init(void)
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mmio_write_32(IOMG_GPIO24, IOMG_MUX_FUNC0);
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}
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void bl2_early_platform_setup(meminfo_t *mem_layout)
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static void hikey_sp804_init(void)
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{
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uint32_t data;
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/* select the clock of dual timer0 */
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data = mmio_read_32(AO_SC_TIMER_EN0);
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while (data & 3) {
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data &= ~3;
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data |= 3 << 16;
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mmio_write_32(AO_SC_TIMER_EN0, data);
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data = mmio_read_32(AO_SC_TIMER_EN0);
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}
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/* enable the pclk of dual timer0 */
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data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
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while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0)) {
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mmio_write_32(AO_SC_PERIPH_CLKEN4, PCLK_TIMER1 | PCLK_TIMER0);
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data = mmio_read_32(AO_SC_PERIPH_CLKSTAT4);
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}
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/* reset dual timer0 */
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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mmio_write_32(AO_SC_PERIPH_RSTEN4, PCLK_TIMER1 | PCLK_TIMER0);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while (!(data & PCLK_TIMER1) || !(data & PCLK_TIMER0));
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/* unreset dual timer0 */
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mmio_write_32(AO_SC_PERIPH_RSTDIS4, PCLK_TIMER1 | PCLK_TIMER0);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while ((data & PCLK_TIMER1) || (data & PCLK_TIMER0));
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sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
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}
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static void hikey_gpio_init(void)
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{
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pl061_gpio_init();
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pl061_gpio_register(GPIO0_BASE, 0);
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pl061_gpio_register(GPIO1_BASE, 1);
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pl061_gpio_register(GPIO2_BASE, 2);
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pl061_gpio_register(GPIO3_BASE, 3);
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pl061_gpio_register(GPIO4_BASE, 4);
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pl061_gpio_register(GPIO5_BASE, 5);
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pl061_gpio_register(GPIO6_BASE, 6);
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pl061_gpio_register(GPIO7_BASE, 7);
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pl061_gpio_register(GPIO8_BASE, 8);
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pl061_gpio_register(GPIO9_BASE, 9);
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pl061_gpio_register(GPIO10_BASE, 10);
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pl061_gpio_register(GPIO11_BASE, 11);
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pl061_gpio_register(GPIO12_BASE, 12);
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pl061_gpio_register(GPIO13_BASE, 13);
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pl061_gpio_register(GPIO14_BASE, 14);
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pl061_gpio_register(GPIO15_BASE, 15);
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pl061_gpio_register(GPIO16_BASE, 16);
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pl061_gpio_register(GPIO17_BASE, 17);
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pl061_gpio_register(GPIO18_BASE, 18);
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pl061_gpio_register(GPIO19_BASE, 19);
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/* Power on indicator LED (USER_LED1). */
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gpio_set_direction(32, GPIO_DIR_OUT); /* LED1 */
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gpio_set_value(32, GPIO_LEVEL_HIGH);
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gpio_set_direction(33, GPIO_DIR_OUT); /* LED2 */
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gpio_set_value(33, GPIO_LEVEL_LOW);
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gpio_set_direction(34, GPIO_DIR_OUT); /* LED3 */
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gpio_set_direction(35, GPIO_DIR_OUT); /* LED4 */
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}
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static void hikey_pmussi_init(void)
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{
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uint32_t data;
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/* Initialize PWR_HOLD GPIO */
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gpio_set_direction(0, GPIO_DIR_OUT);
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gpio_set_value(0, GPIO_LEVEL_LOW);
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/*
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* After reset, PMUSSI stays in reset mode.
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* Now make it out of reset.
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*/
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mmio_write_32(AO_SC_PERIPH_RSTDIS4,
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AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
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do {
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data = mmio_read_32(AO_SC_PERIPH_RSTSTAT4);
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} while (data & AO_SC_PERIPH_RSTDIS4_PRESET_PMUSSI_N);
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/* Set PMUSSI clock latency for read operation. */
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data = mmio_read_32(AO_SC_MCU_SUBSYS_CTRL3);
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data &= ~AO_SC_MCU_SUBSYS_CTRL3_RCLK_MASK;
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data |= AO_SC_MCU_SUBSYS_CTRL3_RCLK_3;
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mmio_write_32(AO_SC_MCU_SUBSYS_CTRL3, data);
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/* enable PMUSSI clock */
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data = AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_CCPU |
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AO_SC_PERIPH_CLKEN5_PCLK_PMUSSI_MCU;
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mmio_write_32(AO_SC_PERIPH_CLKEN5, data);
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data = AO_SC_PERIPH_CLKEN4_PCLK_PMUSSI;
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mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
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gpio_set_value(0, GPIO_LEVEL_HIGH);
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}
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static void hikey_hi6553_init(void)
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{
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uint8_t data;
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mmio_write_8(HI6553_PERI_EN_MARK, 0x1e);
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mmio_write_8(HI6553_NP_REG_ADJ1, 0);
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data = DISABLE6_XO_CLK_CONN | DISABLE6_XO_CLK_NFC |
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DISABLE6_XO_CLK_RF1 | DISABLE6_XO_CLK_RF2;
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mmio_write_8(HI6553_DISABLE6_XO_CLK, data);
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/* configure BUCK0 & BUCK1 */
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mmio_write_8(HI6553_BUCK01_CTRL2, 0x5e);
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mmio_write_8(HI6553_BUCK0_CTRL7, 0x10);
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mmio_write_8(HI6553_BUCK1_CTRL7, 0x10);
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mmio_write_8(HI6553_BUCK0_CTRL5, 0x1e);
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mmio_write_8(HI6553_BUCK1_CTRL5, 0x1e);
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mmio_write_8(HI6553_BUCK0_CTRL1, 0xfc);
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mmio_write_8(HI6553_BUCK1_CTRL1, 0xfc);
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/* configure BUCK2 */
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mmio_write_8(HI6553_BUCK2_REG1, 0x4f);
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mmio_write_8(HI6553_BUCK2_REG5, 0x99);
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mmio_write_8(HI6553_BUCK2_REG6, 0x45);
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mdelay(1);
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mmio_write_8(HI6553_VSET_BUCK2_ADJ, 0x22);
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mdelay(1);
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/* configure BUCK3 */
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mmio_write_8(HI6553_BUCK3_REG3, 0x02);
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mmio_write_8(HI6553_BUCK3_REG5, 0x99);
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mmio_write_8(HI6553_BUCK3_REG6, 0x41);
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mmio_write_8(HI6553_VSET_BUCK3_ADJ, 0x02);
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mdelay(1);
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/* configure BUCK4 */
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mmio_write_8(HI6553_BUCK4_REG2, 0x9a);
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mmio_write_8(HI6553_BUCK4_REG5, 0x99);
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mmio_write_8(HI6553_BUCK4_REG6, 0x45);
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/* configure LDO20 */
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mmio_write_8(HI6553_LDO20_REG_ADJ, 0x50);
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mmio_write_8(HI6553_NP_REG_CHG, 0x0f);
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mmio_write_8(HI6553_CLK_TOP0, 0x06);
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mmio_write_8(HI6553_CLK_TOP3, 0xc0);
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mmio_write_8(HI6553_CLK_TOP4, 0x00);
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/* configure LDO7 & LDO10 for SD slot */
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/* enable LDO7 */
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data = mmio_read_8(HI6553_LDO7_REG_ADJ);
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data = (data & 0xf8) | 0x2;
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mmio_write_8(HI6553_LDO7_REG_ADJ, data);
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mdelay(5);
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mmio_write_8(HI6553_ENABLE2_LDO1_8, 1 << 6);
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mdelay(5);
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/* enable LDO10 */
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data = mmio_read_8(HI6553_LDO10_REG_ADJ);
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data = (data & 0xf8) | 0x5;
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mmio_write_8(HI6553_LDO10_REG_ADJ, data);
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mdelay(5);
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mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 1);
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mdelay(5);
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/* enable LDO15 */
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data = mmio_read_8(HI6553_LDO15_REG_ADJ);
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data = (data & 0xf8) | 0x4;
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mmio_write_8(HI6553_LDO15_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE3_LDO9_16, 1 << 6);
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mdelay(5);
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/* enable LDO19 */
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data = mmio_read_8(HI6553_LDO19_REG_ADJ);
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data |= 0x7;
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mmio_write_8(HI6553_LDO19_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 2);
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mdelay(5);
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/* enable LDO21 */
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data = mmio_read_8(HI6553_LDO21_REG_ADJ);
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data = (data & 0xf8) | 0x3;
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mmio_write_8(HI6553_LDO21_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 4);
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mdelay(5);
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/* enable LDO22 */
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data = mmio_read_8(HI6553_LDO22_REG_ADJ);
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data = (data & 0xf8) | 0x7;
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mmio_write_8(HI6553_LDO22_REG_ADJ, data);
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mmio_write_8(HI6553_ENABLE4_LDO17_22, 1 << 5);
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mdelay(5);
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/* select 32.764KHz */
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mmio_write_8(HI6553_CLK19M2_600_586_EN, 0x01);
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/* Disable vbus_det interrupts */
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data = mmio_read_8(HI6553_IRQ2_MASK);
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data = data | 0x3;
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mmio_write_8(HI6553_IRQ2_MASK, data);
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}
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static void init_mmc0_pll(void)
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{
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unsigned int data;
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/* select SYSPLL as the source of MMC0 */
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/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 5 | 1 << 21);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (!(data & (1 << 5)));
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/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
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mmio_write_32(PERI_SC_CLK_SEL0, 1 << 29);
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do {
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data = mmio_read_32(PERI_SC_CLK_SEL0);
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} while (data & (1 << 13));
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 0));
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & (1 << 0)));
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data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
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data |= 1 << 1;
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mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
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do {
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mmio_write_32(PERI_SC_CLKCFG8BIT1, (1 << 7) | 0xb);
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data = mmio_read_32(PERI_SC_CLKCFG8BIT1);
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} while ((data & 0xb) != 0xb);
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}
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static void reset_mmc0_clk(void)
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{
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unsigned int data;
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/* disable mmc0 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC0);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (data & PERI_CLK0_MMC0);
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/* enable mmc0 bus clock */
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mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC0);
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do {
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data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
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} while (!(data & PERI_CLK0_MMC0));
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/* reset mmc0 clock domain */
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mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC0);
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/* bypass mmc0 clock phase */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
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data |= 3;
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mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
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/* disable low power */
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data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
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data |= 1 << 3;
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mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
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do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
|
||||
} while (!(data & PERI_RST0_MMC0));
|
||||
|
||||
/* unreset mmc0 clock domain */
|
||||
mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC0);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
|
||||
} while (data & PERI_RST0_MMC0);
|
||||
}
|
||||
|
||||
static void init_media_clk(void)
|
||||
{
|
||||
unsigned int data, value;
|
||||
|
||||
data = mmio_read_32(PMCTRL_MEDPLLCTRL);
|
||||
data |= 1;
|
||||
mmio_write_32(PMCTRL_MEDPLLCTRL, data);
|
||||
|
||||
for (;;) {
|
||||
data = mmio_read_32(PMCTRL_MEDPLLCTRL);
|
||||
value = 1 << 28;
|
||||
if ((data & value) == value)
|
||||
break;
|
||||
}
|
||||
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
|
||||
data = 1 << 10;
|
||||
mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
|
||||
}
|
||||
|
||||
static void init_mmc1_pll(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
/* select SYSPLL as the source of MMC1 */
|
||||
/* select SYSPLL as the source of MUX1 (SC_CLK_SEL0) */
|
||||
mmio_write_32(PERI_SC_CLK_SEL0, 1 << 11 | 1 << 27);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_CLK_SEL0);
|
||||
} while (!(data & (1 << 11)));
|
||||
/* select MUX1 as the source of MUX2 (SC_CLK_SEL0) */
|
||||
mmio_write_32(PERI_SC_CLK_SEL0, 1 << 30);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_CLK_SEL0);
|
||||
} while (data & (1 << 14));
|
||||
|
||||
mmio_write_32(PERI_SC_PERIPH_CLKEN0, (1 << 1));
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
|
||||
} while (!(data & (1 << 1)));
|
||||
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CLKEN12);
|
||||
data |= 1 << 2;
|
||||
mmio_write_32(PERI_SC_PERIPH_CLKEN12, data);
|
||||
|
||||
do {
|
||||
/* 1.2GHz / 50 = 24MHz */
|
||||
mmio_write_32(PERI_SC_CLKCFG8BIT2, 0x31 | (1 << 7));
|
||||
data = mmio_read_32(PERI_SC_CLKCFG8BIT2);
|
||||
} while ((data & 0x31) != 0x31);
|
||||
}
|
||||
|
||||
static void reset_mmc1_clk(void)
|
||||
{
|
||||
unsigned int data;
|
||||
|
||||
/* disable mmc1 bus clock */
|
||||
mmio_write_32(PERI_SC_PERIPH_CLKDIS0, PERI_CLK0_MMC1);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
|
||||
} while (data & PERI_CLK0_MMC1);
|
||||
/* enable mmc1 bus clock */
|
||||
mmio_write_32(PERI_SC_PERIPH_CLKEN0, PERI_CLK0_MMC1);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CLKSTAT0);
|
||||
} while (!(data & PERI_CLK0_MMC1));
|
||||
/* reset mmc1 clock domain */
|
||||
mmio_write_32(PERI_SC_PERIPH_RSTEN0, PERI_RST0_MMC1);
|
||||
|
||||
/* bypass mmc1 clock phase */
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CTRL2);
|
||||
data |= 3 << 2;
|
||||
mmio_write_32(PERI_SC_PERIPH_CTRL2, data);
|
||||
|
||||
/* disable low power */
|
||||
data = mmio_read_32(PERI_SC_PERIPH_CTRL13);
|
||||
data |= 1 << 4;
|
||||
mmio_write_32(PERI_SC_PERIPH_CTRL13, data);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
|
||||
} while (!(data & PERI_RST0_MMC1));
|
||||
|
||||
/* unreset mmc0 clock domain */
|
||||
mmio_write_32(PERI_SC_PERIPH_RSTDIS0, PERI_RST0_MMC1);
|
||||
do {
|
||||
data = mmio_read_32(PERI_SC_PERIPH_RSTSTAT0);
|
||||
} while (data & PERI_RST0_MMC1);
|
||||
}
|
||||
|
||||
/* Initialize PLL of both eMMC and SD controllers. */
|
||||
static void hikey_mmc_pll_init(void)
|
||||
{
|
||||
init_mmc0_pll();
|
||||
reset_mmc0_clk();
|
||||
init_media_clk();
|
||||
|
||||
dsb();
|
||||
|
||||
init_mmc1_pll();
|
||||
reset_mmc1_clk();
|
||||
}
|
||||
|
||||
static void hikey_rtc_init(void)
|
||||
{
|
||||
uint32_t data;
|
||||
|
||||
data = mmio_read_32(AO_SC_PERIPH_CLKEN4);
|
||||
data |= AO_SC_PERIPH_RSTDIS4_RESET_RTC0_N;
|
||||
mmio_write_32(AO_SC_PERIPH_CLKEN4, data);
|
||||
}
|
||||
|
||||
void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
|
||||
u_register_t arg3, u_register_t arg4)
|
||||
{
|
||||
/* Initialize the console to provide early debug support */
|
||||
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
|
||||
/*
|
||||
* Allow BL2 to see the whole Trusted RAM.
|
||||
*/
|
||||
bl2_el3_tzram_layout.total_base = BL2_RW_BASE;
|
||||
bl2_el3_tzram_layout.total_size = BL31_LIMIT - BL2_RW_BASE;
|
||||
}
|
||||
|
||||
void bl2_el3_plat_arch_setup(void)
|
||||
{
|
||||
hikey_init_mmu_el3(bl2_el3_tzram_layout.total_base,
|
||||
bl2_el3_tzram_layout.total_size,
|
||||
BL2_RO_BASE,
|
||||
BL2_RO_LIMIT,
|
||||
BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT);
|
||||
}
|
||||
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
dw_mmc_params_t params;
|
||||
|
||||
/* Initialize the console to provide early debug support */
|
||||
console_init(CONSOLE_BASE, PL011_UART_CLK_IN_HZ, PL011_BAUDRATE);
|
||||
hikey_sp804_init();
|
||||
hikey_gpio_init();
|
||||
hikey_pmussi_init();
|
||||
hikey_hi6553_init();
|
||||
|
||||
/* Setup the BL2 memory layout */
|
||||
bl2_tzram_layout = *mem_layout;
|
||||
dsb();
|
||||
hikey_ddr_init();
|
||||
hikey_security_setup();
|
||||
|
||||
/* Clear SRAM since it'll be used by MCU right now. */
|
||||
memset((void *)SRAM_BASE, 0, SRAM_SIZE);
|
||||
clean_dcache_range(SRAM_BASE, SRAM_SIZE);
|
||||
|
||||
sp804_timer_init(SP804_TIMER0_BASE, 10, 192);
|
||||
dsb();
|
||||
hikey_ddr_init();
|
||||
|
||||
hikey_boardid_init();
|
||||
init_acpu_dvfs();
|
||||
hikey_rtc_init();
|
||||
hikey_sd_init();
|
||||
hikey_jumper_init();
|
||||
|
||||
hikey_mmc_pll_init();
|
||||
|
||||
reset_dwmmc_clk();
|
||||
memset(¶ms, 0, sizeof(dw_mmc_params_t));
|
||||
params.reg_base = DWMMC0_BASE;
|
||||
|
|
@ -299,18 +710,3 @@ void bl2_early_platform_setup(meminfo_t *mem_layout)
|
|||
|
||||
hikey_io_setup();
|
||||
}
|
||||
|
||||
void bl2_plat_arch_setup(void)
|
||||
{
|
||||
hikey_init_mmu_el1(bl2_tzram_layout.total_base,
|
||||
bl2_tzram_layout.total_size,
|
||||
BL2_RO_BASE,
|
||||
BL2_RO_LIMIT,
|
||||
BL2_COHERENT_RAM_BASE,
|
||||
BL2_COHERENT_RAM_LIMIT);
|
||||
}
|
||||
|
||||
void bl2_platform_setup(void)
|
||||
{
|
||||
hikey_security_setup();
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1,5 +1,5 @@
|
|||
/*
|
||||
* Copyright (c) 2017, ARM Limited and Contributors. All rights reserved.
|
||||
* Copyright (c) 2017-2018, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
|
@ -65,10 +65,6 @@ static const io_block_dev_spec_t emmc_dev_spec = {
|
|||
.block_size = EMMC_BLOCK_SIZE,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl2_uuid_spec = {
|
||||
.uuid = UUID_TRUSTED_BOOT_FIRMWARE_BL2,
|
||||
};
|
||||
|
||||
static const io_uuid_spec_t bl31_uuid_spec = {
|
||||
.uuid = UUID_EL3_RUNTIME_FIRMWARE_BL31,
|
||||
};
|
||||
|
|
@ -99,11 +95,6 @@ static const struct plat_io_policy policies[] = {
|
|||
(uintptr_t)&emmc_fip_spec,
|
||||
check_emmc
|
||||
},
|
||||
[BL2_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&bl2_uuid_spec,
|
||||
check_fip
|
||||
},
|
||||
[SCP_BL2_IMAGE_ID] = {
|
||||
&fip_dev_handle,
|
||||
(uintptr_t)&scp_bl2_uuid_spec,
|
||||
|
|
|
|||
|
|
@ -80,9 +80,18 @@
|
|||
|
||||
/*
|
||||
* BL2 specific defines.
|
||||
*
|
||||
* Both loader and BL2 region stay in SRAM.
|
||||
* Loader is used to switch Hi6220 SoC from 32-bit to 64-bit mode.
|
||||
*
|
||||
* ++++++++++ 0xF980_0000
|
||||
* + loader +
|
||||
* ++++++++++ 0xF980_1000
|
||||
* + BL2 +
|
||||
* ++++++++++ 0xF981_8000
|
||||
*/
|
||||
#define BL2_BASE (BL1_RW_BASE + 0x8000) /* 0xf981_8000 */
|
||||
#define BL2_LIMIT (BL2_BASE + 0x40000)
|
||||
#define BL2_BASE (BL1_RO_BASE) /* 0xf980_1000 */
|
||||
#define BL2_LIMIT (0xF9818000) /* 0xf981_8000 */
|
||||
|
||||
/*
|
||||
* SCP_BL2 specific defines.
|
||||
|
|
@ -97,8 +106,8 @@
|
|||
/*
|
||||
* BL31 specific defines.
|
||||
*/
|
||||
#define BL31_BASE BL2_LIMIT /* 0xf985_8000 */
|
||||
#define BL31_LIMIT 0xF9898000
|
||||
#define BL31_BASE (0xF9858000) /* 0xf985_8000 */
|
||||
#define BL31_LIMIT (0xF9898000)
|
||||
|
||||
/*
|
||||
* BL3-2 specific defines.
|
||||
|
|
@ -140,7 +149,7 @@
|
|||
#endif /* SPD_none */
|
||||
#endif
|
||||
|
||||
#define NS_BL1U_BASE (BL2_BASE)
|
||||
#define NS_BL1U_BASE (0xf9818000)
|
||||
#define NS_BL1U_SIZE (0x00010000)
|
||||
#define NS_BL1U_LIMIT (NS_BL1U_BASE + NS_BL1U_SIZE)
|
||||
|
||||
|
|
@ -158,15 +167,7 @@
|
|||
#endif
|
||||
|
||||
#ifdef IMAGE_BL2
|
||||
#if LOAD_IMAGE_V2
|
||||
#ifdef SPD_opteed
|
||||
#define MAX_XLAT_TABLES 4
|
||||
#else
|
||||
#define MAX_XLAT_TABLES 3
|
||||
#endif
|
||||
#else
|
||||
#define MAX_XLAT_TABLES 3
|
||||
#endif
|
||||
#endif
|
||||
|
||||
#define MAX_MMAP_REGIONS 16
|
||||
|
|
|
|||
|
|
@ -7,6 +7,9 @@
|
|||
# Enable version2 of image loading
|
||||
LOAD_IMAGE_V2 := 1
|
||||
|
||||
# Non-TF Boot ROM
|
||||
BL2_AT_EL3 := 1
|
||||
|
||||
# On Hikey, the TSP can execute from TZC secure area in DRAM (default)
|
||||
# or SRAM.
|
||||
HIKEY_TSP_RAM_LOCATION := dram
|
||||
|
|
@ -70,13 +73,16 @@ BL1_SOURCES += bl1/tbbr/tbbr_img_desc.c \
|
|||
plat/hisilicon/hikey/hikey_io_storage.c
|
||||
|
||||
BL2_SOURCES += common/desc_image_load.c \
|
||||
drivers/arm/pl061/pl061_gpio.c \
|
||||
drivers/arm/sp804/sp804_delay_timer.c \
|
||||
drivers/delay_timer/delay_timer.c \
|
||||
drivers/gpio/gpio.c \
|
||||
drivers/io/io_block.c \
|
||||
drivers/io/io_fip.c \
|
||||
drivers/io/io_storage.c \
|
||||
drivers/emmc/emmc.c \
|
||||
drivers/synopsys/emmc/dw_mmc.c \
|
||||
lib/cpus/aarch64/cortex_a53.S \
|
||||
plat/hisilicon/hikey/aarch64/hikey_helpers.S \
|
||||
plat/hisilicon/hikey/hikey_bl2_mem_params_desc.c \
|
||||
plat/hisilicon/hikey/hikey_bl2_setup.c \
|
||||
|
|
|
|||
Loading…
Reference in New Issue