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intel: Fix Coverity Scan Defects 

Fix mailbox driver incompatible cast bug and control flow issue that
was flagged by Coverity Scan.

Signed-off-by: Abdul Halim, Muhammad Hadi Asyrafi <muhammad.hadi.asyrafi.abdul.halim@intel.com>
Change-Id: I3f34e98d24e40139d31cf7d5b9b973cd2d981065
This commit is contained in:
Abdul Halim, Muhammad Hadi Asyrafi 2020-02-11 20:17:05 +08:00
parent 513b6165ee
commit a62b47b87a
4 changed files with 21 additions and 21 deletions
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10
plat/intel/soc/common/include/socfpga_mailbox.h
View File

@ -126,21 +126,21 @@ int mailbox_init(void);
void mailbox_set_qspi_close(void);
void mailbox_set_qspi_open(void);
void mailbox_set_qspi_direct(void);
int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args,
int len, int urgent, uint32_t *response, int resp_len);
int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
int len, int urgent);
int mailbox_read_response(int job_id, uint32_t *response, int resp_len);
int mailbox_get_qspi_clock(void);
void mailbox_reset_cold(void);
void mailbox_clear_response(void);
uint32_t intel_mailbox_get_config_status(uint32_t cmd);
int intel_mailbox_get_config_status(uint32_t cmd);
int intel_mailbox_is_fpga_not_ready(void);
int mailbox_rsu_get_spt_offset(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len);
int mailbox_rsu_update(uint32_t *flash_offset);
int mailbox_hps_stage_notify(uint32_t execution_stage);
int mailbox_rsu_update(uint64_t *flash_offset);
int mailbox_hps_stage_notify(uint64_t execution_stage);
#endif /* SOCFPGA_MBOX_H */

20
plat/intel/soc/common/soc/socfpga_mailbox.c
View File

@ -11,7 +11,7 @@
#include "socfpga_mailbox.h"
#include "socfpga_sip_svc.h"
static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint32_t *args,
static int fill_mailbox_circular_buffer(uint32_t header_cmd, uint64_t *args,
int len)
{
uint32_t cmd_free_offset;
@ -167,7 +167,7 @@ int mailbox_poll_response(int job_id, int urgent, uint32_t *response,
}
}
int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint64_t *args,
int len, int urgent)
{
if (urgent)
@ -184,7 +184,7 @@ int mailbox_send_cmd_async(int job_id, unsigned int cmd, uint32_t *args,
return 0;
}
int mailbox_send_cmd(int job_id, unsigned int cmd, uint32_t *args,
int mailbox_send_cmd(int job_id, unsigned int cmd, uint64_t *args,
int len, int urgent, uint32_t *response, int resp_len)
{
int status = 0;
@ -252,7 +252,7 @@ int mailbox_get_qspi_clock(void)
void mailbox_qspi_set_cs(int device_select)
{
uint32_t cs_setting = device_select;
uint64_t cs_setting = device_select;
/* QSPI device select settings at 31:28 */
cs_setting = (cs_setting << 28);
@ -304,13 +304,13 @@ int mailbox_rsu_status(uint32_t *resp_buf, uint32_t resp_buf_len)
return ret;
}
int mailbox_rsu_update(uint32_t *flash_offset)
int mailbox_rsu_update(uint64_t *flash_offset)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_RSU_UPDATE,
(uint32_t *)flash_offset, 2, 0, NULL, 0);
flash_offset, 2, 0, NULL, 0);
}
int mailbox_hps_stage_notify(uint32_t execution_stage)
int mailbox_hps_stage_notify(uint64_t execution_stage)
{
return mailbox_send_cmd(MBOX_JOB_ID, MBOX_HPS_STAGE_NOTIFY,
&execution_stage, 1, 0, NULL, 0);
@ -336,10 +336,10 @@ int mailbox_init(void)
return 0;
}
uint32_t intel_mailbox_get_config_status(uint32_t cmd)
int intel_mailbox_get_config_status(uint32_t cmd)
{
uint32_t status, res;
uint32_t response[6];
int status;
uint32_t res, response[6];
status = mailbox_send_cmd(1, cmd, NULL, 0, 0, response,
sizeof(response) / sizeof(response[0]));

2
plat/intel/soc/common/socfpga_psci.c
View File

@ -135,7 +135,7 @@ extern uint64_t intel_rsu_update_address;
static void __dead2 socfpga_system_reset(void)
{
if (intel_rsu_update_address)
mailbox_rsu_update((uint32_t *)&intel_rsu_update_address);
mailbox_rsu_update(&intel_rsu_update_address);
else
mailbox_reset_cold();

10
plat/intel/soc/common/socfpga_sip_svc.c
View File

@ -61,7 +61,7 @@ struct fpga_config_info fpga_config_buffers[FPGA_CONFIG_BUFFER_SIZE];
static int intel_fpga_sdm_write_buffer(struct fpga_config_info *buffer)
{
uint32_t args[3];
uint64_t args[3];
while (max_blocks > 0 && buffer->size > buffer->size_written) {
args[0] = (1<<8);
@ -256,7 +256,7 @@ static bool is_address_in_ddr_range(uint64_t addr, uint64_t size)
{
if (size > (UINT64_MAX - addr))
return false;
if (addr < DRAM_BASE)
if (addr < BL31_LIMIT)
return false;
if (addr + size > DRAM_BASE + DRAM_SIZE)
return false;
@ -387,7 +387,7 @@ static uint32_t intel_rsu_update(uint64_t update_address)
static uint32_t intel_rsu_notify(uint64_t execution_stage)
{
if (mailbox_hps_stage_notify((uint32_t)execution_stage) < 0)
if (mailbox_hps_stage_notify(execution_stage) < 0)
return INTEL_SIP_SMC_STATUS_ERROR;
return INTEL_SIP_SMC_STATUS_OK;
@ -404,7 +404,7 @@ static uint32_t intel_rsu_retry_counter(uint32_t *respbuf, uint32_t respbuf_sz,
}
/* Mailbox services */
static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint32_t *args, int len,
static uint32_t intel_mbox_send_cmd(uint32_t cmd, uint64_t *args, int len,
int urgent, uint32_t *response,
int resp_len, int *mbox_status,
int *len_in_resp)
@ -542,7 +542,7 @@ uintptr_t sip_smc_handler(uint32_t smc_fid,
case INTEL_SIP_SMC_MBOX_SEND_CMD:
x5 = SMC_GET_GP(handle, CTX_GPREG_X5);
x6 = SMC_GET_GP(handle, CTX_GPREG_X6);
status = intel_mbox_send_cmd(x1, (uint32_t *)x2, x3, x4,
status = intel_mbox_send_cmd(x1, (uint64_t *)x2, x3, x4,
(uint32_t *)x5, x6, &mbox_status,
&len_in_resp);
SMC_RET4(handle, status, mbox_status, x5, len_in_resp);