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errata: workaround for Cortex-A710 errata 2081180 

Cortex-A710 erratum 2081180 is a Cat B erratum present in r0p0, r1p0,
and r2p0 of the Cortex-A710 processor core, and it is still open.

A710 SDEN: https://developer.arm.com/documentation/SDEN1775101/1000

Signed-off-by: nayanpatel-arm <nayankumar.patel@arm.com>
Change-Id: I1e8c2bc3d8dc326947ccfd91daf9083d666b2542
This commit is contained in:
nayanpatel-arm 2021-08-25 17:35:15 -07:00
parent fbcf54aeb9
commit a64bcc2b45
3 changed files with 61 additions and 0 deletions
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4
docs/design/cpu-specific-build-macros.rst
View File

@ -365,6 +365,10 @@ For Cortex-A710, the following errata build flags are defined :
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.
- ``ERRATA_A710_2081180``: This applies errata 2081180 workaround to
Cortex-A710 CPU. This needs to be enabled only for revisions r0p0, r1p0 and
r2p0 of the CPU. It is still open.
DSU Errata Workarounds
----------------------

49
lib/cpus/aarch64/cortex_a710.S
View File

@ -64,6 +64,49 @@ func check_errata_1987031
b cpu_rev_var_ls
endfunc check_errata_1987031
/* --------------------------------------------------
* Errata Workaround for Cortex-A710 Erratum 2081180.
* This applies to revision r0p0, r1p0 and r2p0 of Cortex-A710.
* It is still open.
* Inputs:
* x0: variant[4:7] and revision[0:3] of current cpu.
* Shall clobber: x0-x17
* --------------------------------------------------
*/
func errata_a710_2081180_wa
/* Check revision. */
mov x17, x30
bl check_errata_2081180
cbz x0, 1f
/* Apply instruction patching sequence */
ldr x0,=0x3
msr S3_6_c15_c8_0,x0
ldr x0,=0xF3A08002
msr S3_6_c15_c8_2,x0
ldr x0,=0xFFF0F7FE
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003FF
msr S3_6_c15_c8_1,x0
ldr x0,=0x4
msr S3_6_c15_c8_0,x0
ldr x0,=0xBF200000
msr S3_6_c15_c8_2,x0
ldr x0,=0xFFEF0000
msr S3_6_c15_c8_3,x0
ldr x0,=0x10002001003F3
msr S3_6_c15_c8_1,x0
isb
1:
ret x17
endfunc errata_a710_2081180_wa
func check_errata_2081180
/* Applies to r0p0, r1p0 and r2p0 */
mov x1, #0x20
b cpu_rev_var_ls
endfunc check_errata_2081180
/* ----------------------------------------------------
* HW will do the cache maintenance while powering down
* ----------------------------------------------------
@ -95,6 +138,7 @@ func cortex_a710_errata_report
* checking functions of each errata.
*/
report_errata ERRATA_A710_1987031, cortex_a710, 1987031
report_errata ERRATA_A710_2081180, cortex_a710, 2081180
ldp x8, x30, [sp], #16
ret
@ -115,6 +159,11 @@ func cortex_a710_reset_func
bl errata_a710_1987031_wa
#endif
#if ERRATA_A710_2081180
mov x0, x18
bl errata_a710_2081180_wa
#endif
isb
ret x19
endfunc cortex_a710_reset_func

8
lib/cpus/cpu-ops.mk
View File

@ -409,6 +409,10 @@ ERRATA_V1_2139242 ?=0
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_1987031 ?=0
# Flag to apply erratum 2081180 workaround during reset. This erratum applies
# to revisions r0p0, r1p0 and r2p0 of the Cortex-A710 cpu and is still open.
ERRATA_A710_2081180 ?=0
# Flag to apply DSU erratum 798953. This erratum applies to DSUs revision r0p0.
# Applying the workaround results in higher DSU power consumption on idle.
ERRATA_DSU_798953 ?=0
@ -750,6 +754,10 @@ $(eval $(call add_define,ERRATA_V1_2139242))
$(eval $(call assert_boolean,ERRATA_A710_1987031))
$(eval $(call add_define,ERRATA_A710_1987031))
# Process ERRATA_A710_2081180 flag
$(eval $(call assert_boolean,ERRATA_A710_2081180))
$(eval $(call add_define,ERRATA_A710_2081180))
# Process ERRATA_DSU_798953 flag
$(eval $(call assert_boolean,ERRATA_DSU_798953))
$(eval $(call add_define,ERRATA_DSU_798953))