Merge changes from topic "spm-secondary-cores" into integration
* changes: SPMC: embed secondary core ep info into to SPMC context SPMC: manifest changes to support multicore boot SPMD: secondary cores PM on and off SPD hooks relayed to SPMC SPMD: handle SPMC message to register secondary core entry point SPMD: introduce SPMC to SPMD messages SPMD: register the SPD PM hooks SPMD: add generic SPD PM handlers SPMD: enhance SPMC internal boot states SPMD: entry point info get helper
This commit is contained in:
Olivier Deprez
TrustedFirmware Code Review
commit
a6ab1ae39c
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@ -138,4 +138,43 @@
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*/
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#define FFA_PARAM_MBZ U(0x0)
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/*
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* Maximum FF-A endpoint id value
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*/
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#define FFA_ENDPOINT_ID_MAX U(1 << 16)
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/*
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* Mask for source and destination endpoint id in
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* a direct message request/response.
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*/
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#define FFA_DIRECT_MSG_ENDPOINT_ID_MASK U(0xffff)
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/*
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* Bit shift for destination endpoint id in a direct message request/response.
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*/
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#define FFA_DIRECT_MSG_DESTINATION_SHIFT U(0)
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/*
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* Bit shift for source endpoint id in a direct message request/response.
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*/
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#define FFA_DIRECT_MSG_SOURCE_SHIFT U(16)
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/******************************************************************************
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* ffa_endpoint_destination
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*****************************************************************************/
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static inline uint16_t ffa_endpoint_destination(unsigned int ep)
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{
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return (ep >> FFA_DIRECT_MSG_DESTINATION_SHIFT) &
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FFA_DIRECT_MSG_ENDPOINT_ID_MASK;
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}
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/******************************************************************************
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* ffa_endpoint_source
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*****************************************************************************/
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static inline uint16_t ffa_endpoint_source(unsigned int ep)
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{
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return (ep >> FFA_DIRECT_MSG_SOURCE_SHIFT) &
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FFA_DIRECT_MSG_ENDPOINT_ID_MASK;
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}
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#endif /* FFA_SVC_H */
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@ -44,7 +44,7 @@ typedef struct spm_core_manifest_sect_attribute {
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uint32_t binary_size;
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/*
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* ID of the SPMD (mandatory)
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* ID of the SPMC (mandatory)
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*/
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uint16_t spmc_id;
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@ -5,6 +5,14 @@
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*/
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/dts-v1/;
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#define AFF 00
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#include "fvp-defs.dtsi"
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#undef POST
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#define POST \
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enable-method = "psci"; \
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};
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/ {
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compatible = "arm,ffa-core-manifest-1.0";
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#address-cells = <2>;
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@ -17,6 +25,7 @@
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exec_state = <0x0>;
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load_address = <0x0 0x6000000>;
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entrypoint = <0x0 0x6000000>;
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binary_size = <0x80000>;
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};
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chosen {
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@ -51,22 +60,15 @@
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#address-cells = <0x2>;
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#size-cells = <0x0>;
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cpu-map {
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cluster0 {
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core0 {
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cpu = <0x2>;
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};
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};
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};
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,armv8";
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reg = <0x0 0x0>;
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enable-method = "psci";
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next-level-cache = <0xc>;
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phandle = <0x2>;
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};
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CPU_0
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/* SPM(Hafnium) requires secondary cpu nodes are declared in descending order */
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CPU_7
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CPU_6
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CPU_5
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CPU_4
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CPU_3
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CPU_2
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CPU_1
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};
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memory@60000000 {
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@ -10,6 +10,7 @@ endif
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SPMD_SOURCES += $(addprefix services/std_svc/spmd/, \
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${ARCH}/spmd_helpers.S \
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spmd_pm.c \
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spmd_main.c)
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# Let the top-level Makefile know that we intend to include a BL32 image
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@ -41,14 +41,36 @@ static spmc_manifest_attribute_t spmc_attrs;
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******************************************************************************/
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static entry_point_info_t *spmc_ep_info;
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/*******************************************************************************
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* SPM Core context on CPU based on mpidr.
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******************************************************************************/
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spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr)
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{
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return &spm_core_context[plat_core_pos_by_mpidr(mpidr)];
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}
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/*******************************************************************************
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* SPM Core context on current CPU get helper.
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******************************************************************************/
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spmd_spm_core_context_t *spmd_get_context(void)
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{
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unsigned int linear_id = plat_my_core_pos();
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return spmd_get_context_by_mpidr(read_mpidr());
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}
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return &spm_core_context[linear_id];
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/*******************************************************************************
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* SPM Core entry point information get helper.
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******************************************************************************/
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entry_point_info_t *spmd_spmc_ep_info_get(void)
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{
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return spmc_ep_info;
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}
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/*******************************************************************************
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* SPM Core ID getter.
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******************************************************************************/
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uint16_t spmd_spmc_id_get(void)
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{
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return spmc_attrs.spmc_id;
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}
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/*******************************************************************************
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@ -125,9 +147,19 @@ static int32_t spmd_init(void)
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{
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spmd_spm_core_context_t *ctx = spmd_get_context();
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uint64_t rc;
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unsigned int linear_id = plat_my_core_pos();
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unsigned int core_id;
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VERBOSE("SPM Core init start.\n");
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ctx->state = SPMC_STATE_RESET;
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ctx->state = SPMC_STATE_ON_PENDING;
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/* Set the SPMC context state on other CPUs to OFF */
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for (core_id = 0U; core_id < PLATFORM_CORE_COUNT; core_id++) {
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if (core_id != linear_id) {
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spm_core_context[core_id].state = SPMC_STATE_OFF;
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spm_core_context[core_id].secondary_ep.entry_point = 0UL;
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}
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}
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rc = spmd_spm_core_sync_entry(ctx);
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if (rc != 0ULL) {
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@ -135,7 +167,8 @@ static int32_t spmd_init(void)
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return 0;
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}
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ctx->state = SPMC_STATE_IDLE;
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ctx->state = SPMC_STATE_ON;
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VERBOSE("SPM Core init end.\n");
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return 1;
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@ -248,6 +281,9 @@ static int spmd_spmc_init(void *pm_addr)
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INFO("SPM Core setup done.\n");
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/* Register power management hooks with PSCI */
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psci_register_spd_pm_hook(&spmd_pm);
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/* Register init function for deferred init. */
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bl31_register_bl32_init(&spmd_init);
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@ -301,8 +337,8 @@ static uint64_t spmd_smc_forward(uint32_t smc_fid,
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uint64_t x4,
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void *handle)
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{
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uint32_t secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
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uint32_t secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
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unsigned int secure_state_in = (secure_origin) ? SECURE : NON_SECURE;
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unsigned int secure_state_out = (!secure_origin) ? SECURE : NON_SECURE;
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/* Save incoming security state */
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cm_el1_sysregs_context_save(secure_state_in);
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@ -334,6 +370,46 @@ static uint64_t spmd_ffa_error_return(void *handle, int error_code)
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FFA_PARAM_MBZ, FFA_PARAM_MBZ);
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}
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/*******************************************************************************
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* spmd_check_address_in_binary_image
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******************************************************************************/
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bool spmd_check_address_in_binary_image(uint64_t address)
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{
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assert(!check_uptr_overflow(spmc_attrs.load_address, spmc_attrs.binary_size));
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return ((address >= spmc_attrs.load_address) &&
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(address < (spmc_attrs.load_address + spmc_attrs.binary_size)));
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}
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/******************************************************************************
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* spmd_is_spmc_message
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*****************************************************************************/
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static bool spmd_is_spmc_message(unsigned int ep)
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{
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return ((ffa_endpoint_destination(ep) == SPMD_DIRECT_MSG_ENDPOINT_ID)
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&& (ffa_endpoint_source(ep) == spmc_attrs.spmc_id));
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}
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/******************************************************************************
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* spmd_handle_spmc_message
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*****************************************************************************/
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static int spmd_handle_spmc_message(unsigned long long msg,
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unsigned long long parm1, unsigned long long parm2,
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unsigned long long parm3, unsigned long long parm4)
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{
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VERBOSE("%s %llx %llx %llx %llx %llx\n", __func__,
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msg, parm1, parm2, parm3, parm4);
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switch (msg) {
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case SPMD_DIRECT_MSG_SET_ENTRY_POINT:
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return spmd_pm_secondary_core_set_ep(parm1, parm2, parm3);
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default:
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break;
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}
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return -EINVAL;
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}
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/*******************************************************************************
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* This function handles all SMCs in the range reserved for FFA. Each call is
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* either forwarded to the other security state or handled by the SPM dispatcher
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@ -367,7 +443,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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* this CPU. If so, then indicate that the SPM Core initialised
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* unsuccessfully.
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*/
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if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
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if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
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spmd_spm_core_sync_exit(x2);
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}
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@ -451,6 +527,35 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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break; /* not reached */
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case FFA_MSG_SEND_DIRECT_REQ_SMC32:
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if (secure_origin && spmd_is_spmc_message(x1)) {
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ret = spmd_handle_spmc_message(x3, x4,
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SMC_GET_GP(handle, CTX_GPREG_X5),
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SMC_GET_GP(handle, CTX_GPREG_X6),
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SMC_GET_GP(handle, CTX_GPREG_X7));
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SMC_RET8(handle, FFA_SUCCESS_SMC32,
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FFA_TARGET_INFO_MBZ, ret,
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FFA_PARAM_MBZ, FFA_PARAM_MBZ,
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FFA_PARAM_MBZ, FFA_PARAM_MBZ,
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FFA_PARAM_MBZ);
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} else {
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/* Forward direct message to the other world */
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return spmd_smc_forward(smc_fid, secure_origin,
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x1, x2, x3, x4, handle);
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}
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break; /* Not reached */
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case FFA_MSG_SEND_DIRECT_RESP_SMC32:
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if (secure_origin && spmd_is_spmc_message(x1)) {
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spmd_spm_core_sync_exit(0);
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} else {
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/* Forward direct message to the other world */
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return spmd_smc_forward(smc_fid, secure_origin,
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x1, x2, x3, x4, handle);
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}
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break; /* Not reached */
|
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|
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case FFA_RX_RELEASE:
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case FFA_RXTX_MAP_SMC32:
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case FFA_RXTX_MAP_SMC64:
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|
|
@ -466,9 +571,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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case FFA_PARTITION_INFO_GET:
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case FFA_MSG_SEND:
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case FFA_MSG_SEND_DIRECT_REQ_SMC32:
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case FFA_MSG_SEND_DIRECT_REQ_SMC64:
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case FFA_MSG_SEND_DIRECT_RESP_SMC32:
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case FFA_MSG_SEND_DIRECT_RESP_SMC64:
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case FFA_MEM_DONATE_SMC32:
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case FFA_MEM_DONATE_SMC64:
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||||
|
|
@ -500,7 +603,7 @@ uint64_t spmd_smc_handler(uint32_t smc_fid,
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|||
* this CPU from the Secure world. If so, then indicate that the
|
||||
* SPM Core initialised successfully.
|
||||
*/
|
||||
if (secure_origin && (ctx->state == SPMC_STATE_RESET)) {
|
||||
if (secure_origin && (ctx->state == SPMC_STATE_ON_PENDING)) {
|
||||
spmd_spm_core_sync_exit(0);
|
||||
}
|
||||
|
||||
|
|
|
|||
|
|
@ -0,0 +1,156 @@
|
|||
/*
|
||||
* Copyright (c) 2020, ARM Limited and Contributors. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <errno.h>
|
||||
#include <lib/el3_runtime/context_mgmt.h>
|
||||
#include "spmd_private.h"
|
||||
|
||||
/*******************************************************************************
|
||||
* spmd_build_spmc_message
|
||||
*
|
||||
* Builds an SPMD to SPMC direct message request.
|
||||
******************************************************************************/
|
||||
static void spmd_build_spmc_message(gp_regs_t *gpregs, unsigned long long message)
|
||||
{
|
||||
write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32);
|
||||
write_ctx_reg(gpregs, CTX_GPREG_X1,
|
||||
(SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) |
|
||||
spmd_spmc_id_get());
|
||||
write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_PARAM_MBZ);
|
||||
write_ctx_reg(gpregs, CTX_GPREG_X3, message);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* spmd_pm_secondary_core_set_ep
|
||||
******************************************************************************/
|
||||
int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
|
||||
uintptr_t entry_point, unsigned long long context)
|
||||
{
|
||||
int id = plat_core_pos_by_mpidr(mpidr);
|
||||
|
||||
if ((id < 0) || (id >= PLATFORM_CORE_COUNT)) {
|
||||
ERROR("%s inconsistent MPIDR (%llx)\n", __func__, mpidr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/*
|
||||
* Check entry_point address is a PA within
|
||||
* load_address <= entry_point < load_address + binary_size
|
||||
*/
|
||||
if (!spmd_check_address_in_binary_image(entry_point)) {
|
||||
ERROR("%s entry point is not within image boundaries (%llx)\n",
|
||||
__func__, mpidr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
spmd_spm_core_context_t *ctx = spmd_get_context_by_mpidr(mpidr);
|
||||
spmd_pm_secondary_ep_t *secondary_ep = &ctx->secondary_ep;
|
||||
if (secondary_ep->locked) {
|
||||
ERROR("%s entry locked (%llx)\n", __func__, mpidr);
|
||||
return -EINVAL;
|
||||
}
|
||||
|
||||
/* Fill new entry to corresponding secondary core id and lock it */
|
||||
secondary_ep->entry_point = entry_point;
|
||||
secondary_ep->context = context;
|
||||
secondary_ep->locked = true;
|
||||
|
||||
VERBOSE("%s %d %llx %lx %llx\n",
|
||||
__func__, id, mpidr, entry_point, context);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* This CPU has been turned on. Enter SPMC to initialise S-EL1 or S-EL2. As part
|
||||
* of the SPMC initialization path, they will initialize any SPs that they
|
||||
* manage. Entry into SPMC is done after initialising minimal architectural
|
||||
* state that guarantees safe execution.
|
||||
******************************************************************************/
|
||||
static void spmd_cpu_on_finish_handler(u_register_t unused)
|
||||
{
|
||||
entry_point_info_t *spmc_ep_info = spmd_spmc_ep_info_get();
|
||||
spmd_spm_core_context_t *ctx = spmd_get_context();
|
||||
unsigned int linear_id = plat_my_core_pos();
|
||||
uint64_t rc;
|
||||
|
||||
assert(ctx != NULL);
|
||||
assert(ctx->state != SPMC_STATE_ON);
|
||||
assert(spmc_ep_info != NULL);
|
||||
|
||||
/*
|
||||
* TODO: this might require locking the spmc_ep_info structure,
|
||||
* or provisioning one structure per cpu
|
||||
*/
|
||||
if (ctx->secondary_ep.entry_point == 0UL) {
|
||||
goto exit;
|
||||
}
|
||||
|
||||
spmc_ep_info->pc = ctx->secondary_ep.entry_point;
|
||||
cm_setup_context(&ctx->cpu_ctx, spmc_ep_info);
|
||||
write_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), CTX_GPREG_X0,
|
||||
ctx->secondary_ep.context);
|
||||
|
||||
/* Mark CPU as initiating ON operation */
|
||||
ctx->state = SPMC_STATE_ON_PENDING;
|
||||
|
||||
rc = spmd_spm_core_sync_entry(ctx);
|
||||
if (rc != 0ULL) {
|
||||
ERROR("%s failed (%llu) on CPU%u\n", __func__, rc,
|
||||
linear_id);
|
||||
ctx->state = SPMC_STATE_OFF;
|
||||
return;
|
||||
}
|
||||
|
||||
exit:
|
||||
ctx->state = SPMC_STATE_ON;
|
||||
|
||||
VERBOSE("CPU %u on!\n", linear_id);
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* spmd_cpu_off_handler
|
||||
******************************************************************************/
|
||||
static int32_t spmd_cpu_off_handler(u_register_t unused)
|
||||
{
|
||||
spmd_spm_core_context_t *ctx = spmd_get_context();
|
||||
unsigned int linear_id = plat_my_core_pos();
|
||||
int64_t rc;
|
||||
|
||||
assert(ctx != NULL);
|
||||
assert(ctx->state != SPMC_STATE_OFF);
|
||||
|
||||
if (ctx->secondary_ep.entry_point == 0UL) {
|
||||
goto exit;
|
||||
}
|
||||
|
||||
/* Build an SPMD to SPMC direct message request. */
|
||||
spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx), PSCI_CPU_OFF);
|
||||
|
||||
rc = spmd_spm_core_sync_entry(ctx);
|
||||
if (rc != 0ULL) {
|
||||
ERROR("%s failed (%llu) on CPU%u\n", __func__, rc, linear_id);
|
||||
}
|
||||
|
||||
/* TODO expect FFA_DIRECT_MSG_RESP returned from SPMC */
|
||||
|
||||
exit:
|
||||
ctx->state = SPMC_STATE_OFF;
|
||||
|
||||
VERBOSE("CPU %u off!\n", linear_id);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure populated by the SPM Dispatcher to perform any bookkeeping before
|
||||
* PSCI executes a power mgmt. operation.
|
||||
******************************************************************************/
|
||||
const spd_pm_ops_t spmd_pm = {
|
||||
.svc_on_finish = spmd_cpu_on_finish_handler,
|
||||
.svc_off = spmd_cpu_off_handler
|
||||
};
|
||||
|
|
@ -30,14 +30,24 @@
|
|||
#define SPMD_C_RT_CTX_ENTRIES (SPMD_C_RT_CTX_SIZE >> DWORD_SHIFT)
|
||||
|
||||
#ifndef __ASSEMBLER__
|
||||
#include <services/ffa_svc.h>
|
||||
#include <stdint.h>
|
||||
#include <lib/psci/psci_lib.h>
|
||||
#include <plat/common/platform.h>
|
||||
#include <services/ffa_svc.h>
|
||||
|
||||
typedef enum spmc_state {
|
||||
SPMC_STATE_RESET = 0,
|
||||
SPMC_STATE_IDLE
|
||||
SPMC_STATE_OFF,
|
||||
SPMC_STATE_ON_PENDING,
|
||||
SPMC_STATE_ON
|
||||
} spmc_state_t;
|
||||
|
||||
typedef struct spmd_pm_secondary_ep {
|
||||
uintptr_t entry_point;
|
||||
uintptr_t context;
|
||||
bool locked;
|
||||
} spmd_pm_secondary_ep_t;
|
||||
|
||||
/*
|
||||
* Data structure used by the SPM dispatcher (SPMD) in EL3 to track context of
|
||||
* the SPM core (SPMC) at the next lower EL.
|
||||
|
|
@ -46,16 +56,20 @@ typedef struct spmd_spm_core_context {
|
|||
uint64_t c_rt_ctx;
|
||||
cpu_context_t cpu_ctx;
|
||||
spmc_state_t state;
|
||||
spmd_pm_secondary_ep_t secondary_ep;
|
||||
} spmd_spm_core_context_t;
|
||||
|
||||
/*
|
||||
* Reserve ID for NS physical FFA Endpoint.
|
||||
*/
|
||||
#define FFA_NS_ENDPOINT_ID U(0)
|
||||
#define FFA_NS_ENDPOINT_ID U(0)
|
||||
|
||||
/* Mask and shift to check valid secure FFA Endpoint ID. */
|
||||
#define SPMC_SECURE_ID_MASK U(1)
|
||||
#define SPMC_SECURE_ID_SHIFT U(15)
|
||||
/* Mask and shift to check valid secure FF-A Endpoint ID. */
|
||||
#define SPMC_SECURE_ID_MASK U(1)
|
||||
#define SPMC_SECURE_ID_SHIFT U(15)
|
||||
|
||||
#define SPMD_DIRECT_MSG_ENDPOINT_ID U(FFA_ENDPOINT_ID_MAX - 1)
|
||||
#define SPMD_DIRECT_MSG_SET_ENTRY_POINT U(1)
|
||||
|
||||
/* Functions used to enter/exit SPMC synchronously */
|
||||
uint64_t spmd_spm_core_sync_entry(spmd_spm_core_context_t *ctx);
|
||||
|
|
@ -65,9 +79,25 @@ __dead2 void spmd_spm_core_sync_exit(uint64_t rc);
|
|||
uint64_t spmd_spm_core_enter(uint64_t *c_rt_ctx);
|
||||
void __dead2 spmd_spm_core_exit(uint64_t c_rt_ctx, uint64_t ret);
|
||||
|
||||
/* SPMD SPD power management handlers */
|
||||
extern const spd_pm_ops_t spmd_pm;
|
||||
|
||||
/* SPMC entry point information helper */
|
||||
entry_point_info_t *spmd_spmc_ep_info_get(void);
|
||||
|
||||
/* SPMC ID getter */
|
||||
uint16_t spmd_spmc_id_get(void);
|
||||
|
||||
/* SPMC context on CPU based on mpidr */
|
||||
spmd_spm_core_context_t *spmd_get_context_by_mpidr(uint64_t mpidr);
|
||||
|
||||
/* SPMC context on current CPU get helper */
|
||||
spmd_spm_core_context_t *spmd_get_context(void);
|
||||
|
||||
int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
|
||||
uintptr_t entry_point, unsigned long long context);
|
||||
bool spmd_check_address_in_binary_image(uint64_t address);
|
||||
|
||||
#endif /* __ASSEMBLER__ */
|
||||
|
||||
#endif /* SPMD_PRIVATE_H */
|
||||
|
|
|
|||
Loading…
Reference in New Issue