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Merge changes Ie7c0eaf2,I11d882f3,I3f173ac4,If1fa12bf,I3e3a202f, ... into integration 

* changes:
  feat(plat/rcar3): keep RWDT enabled
  feat(drivers/rcar3): add extra offset if booting B-side
  feat(plat/rcar3): modify LifeC register setting for R-Car D3
  feat(plat/rcar3): modify SWDT counter setting for R-Car D3
  feat(plat/rcar3): update DDR setting for R-Car D3
  feat(plat/rcar3): remove access to RMSTPCRn registers in R-Car D3
  feat(plat/rcar3): add process of SSCG setting for R-Car D3
  feat(plat/rcar3): add process to back up X6 and X7 register's value
  feat(plat/rcar3): modify operation register from SYSCISR to SYSCISCR
  feat(plat/rcar3): add SYSCEXTMASK bit set/clear in scu_power_up
  feat(plat/rcar3): change the memory map for OP-TEE
  feat(plat/rcar3): use PRR cut to determine DRAM size on M3
  feat(plat/rcar3): apply ERRATA_A53_1530924 and ERRATA_A57_1319537
  fix(plat/rcar3): fix disabling MFIS write protection for R-Car D3
  fix(plat/rcar3): fix eMMC boot support for R-Car D3
  fix(plat/rcar3): fix version judgment for R-Car D3
  fix(plat/rcar3): fix source file to make about GICv2
  fix(drivers/rcar3): console: fix a return value of console_rcar_init
This commit is contained in:
Manish Pandey 2021-10-05 16:50:23 +02:00 committed by TrustedFirmware Code Review
parent 64e8ac6f2a 899108601a
commit a6db44ad16
14 changed files with 164 additions and 87 deletions
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4
drivers/renesas/common/console/rcar_console.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -63,7 +63,7 @@ endfunc console_rcar_register
* ---------------------------------------------
*/
func console_rcar_init
mov w0, #0
mov w0, #1
ret
endfunc console_rcar_init

74
drivers/renesas/common/ddr/ddr_a/ddr_init_d3.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2019, Renesas Electronics Corporation.
* Copyright (c) 2015-2021, Renesas Electronics Corporation.
* All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
@ -11,7 +11,11 @@
#include "rcar_def.h"
#include "../ddr_regs.h"
#define RCAR_DDR_VERSION "rev.0.01"
#define RCAR_DDR_VERSION "rev.0.02"
/* Average periodic refresh interval[ns]. Support 3900,7800 */
#define REFRESH_RATE 3900
#if RCAR_LSI != RCAR_D3
#error "Don't have DDR initialize routine."
@ -44,7 +48,7 @@ static void init_ddr_d3_1866(void)
mmio_write_32(DBSC_DBTR16, 0x09210507);
mmio_write_32(DBSC_DBTR17, 0x040E0000);
mmio_write_32(DBSC_DBTR18, 0x00000200);
mmio_write_32(DBSC_DBTR19, 0x012B004B);
mmio_write_32(DBSC_DBTR19, 0x0129004B);
mmio_write_32(DBSC_DBTR20, 0x020000FB);
mmio_write_32(DBSC_DBTR21, 0x00040004);
mmio_write_32(DBSC_DBBL, 0x00000000);
@ -54,8 +58,8 @@ static void init_ddr_d3_1866(void)
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
mmio_write_32(DBSC_SCFCTST0, 0x0D020D04);
mmio_write_32(DBSC_SCFCTST1, 0x0306040C);
mmio_write_32(DBSC_SCFCTST0, 0x0C050B03);
mmio_write_32(DBSC_SCFCTST1, 0x0305030C);
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01000001);
@ -101,7 +105,9 @@ static void init_ddr_d3_1866(void)
;
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
mmio_write_32(DBSC_DBPDRGD_0, 0x0A206F89);
mmio_write_32(DBSC_DBPDRGD_0,
(uint32_t) (REFRESH_RATE * 928 / 125) - 400
+ 0x0A300000);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
@ -117,7 +123,11 @@ static void init_ddr_d3_1866(void)
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
if (REFRESH_RATE > 3900) {
mmio_write_32(DBSC_DBPDRGD_0, 0x00000020);
} else {
mmio_write_32(DBSC_DBPDRGD_0, 0x000000A0);
}
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
@ -225,8 +235,10 @@ static void init_ddr_d3_1866(void)
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
r2 = mmio_read_32(DBSC_DBPDRGD_0);
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
r2 = mmio_read_32(DBSC_DBPDRGD_0);
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
@ -296,8 +308,10 @@ static void init_ddr_d3_1866(void)
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
mmio_write_32(DBSC_DBRFCNF1, 0x00080E23);
mmio_write_32(DBSC_DBCALCNF,
(uint32_t) (64000000 / REFRESH_RATE) + 0x01000000);
mmio_write_32(DBSC_DBRFCNF1,
(uint32_t) (REFRESH_RATE * 116 / 125) + 0x00080000);
mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
mmio_write_32(DBSC_DBRFEN, 0x00000001);
@ -346,6 +360,19 @@ static void init_ddr_d3_1600(void)
{
uint32_t i, r2, r3, r5, r6, r7, r12;
mmio_write_32(CPG_CPGWPR, 0x5A5AFFFF);
mmio_write_32(CPG_CPGWPCR, 0xA5A50000);
mmio_write_32(CPG_SRCR4, 0x20000000);
mmio_write_32(0xE61500DC, 0xe2200000);
while (!(mmio_read_32(CPG_PLLECR) & BIT(11)))
;
mmio_write_32(CPG_SRSTCLR4, 0x20000000);
mmio_write_32(CPG_CPGWPCR, 0xA5A50001);
mmio_write_32(DBSC_DBSYSCNT0, 0x00001234);
mmio_write_32(DBSC_DBKIND, 0x00000007);
mmio_write_32(DBSC_DBMEMCONF_0_0, 0x0f030a01);
@ -363,14 +390,14 @@ static void init_ddr_d3_1600(void)
mmio_write_32(DBSC_DBTR10, 0x0000000C);
mmio_write_32(DBSC_DBTR11, 0x0000000A);
mmio_write_32(DBSC_DBTR12, 0x00120012);
mmio_write_32(DBSC_DBTR13, 0x000000D0);
mmio_write_32(DBSC_DBTR13, 0x000000CE);
mmio_write_32(DBSC_DBTR14, 0x00140005);
mmio_write_32(DBSC_DBTR15, 0x00050004);
mmio_write_32(DBSC_DBTR16, 0x071F0305);
mmio_write_32(DBSC_DBTR17, 0x040C0000);
mmio_write_32(DBSC_DBTR18, 0x00000200);
mmio_write_32(DBSC_DBTR19, 0x01000040);
mmio_write_32(DBSC_DBTR20, 0x020000D8);
mmio_write_32(DBSC_DBTR20, 0x020000D6);
mmio_write_32(DBSC_DBTR21, 0x00040004);
mmio_write_32(DBSC_DBBL, 0x00000000);
mmio_write_32(DBSC_DBODT0, 0x00000001);
@ -379,8 +406,8 @@ static void init_ddr_d3_1600(void)
mmio_write_32(DBSC_DBDFICNT_0, 0x00000010);
mmio_write_32(DBSC_DBBCAMDIS, 0x00000001);
mmio_write_32(DBSC_DBSCHRW1, 0x00000046);
mmio_write_32(DBSC_SCFCTST0, 0x0D020C04);
mmio_write_32(DBSC_SCFCTST1, 0x0305040C);
mmio_write_32(DBSC_SCFCTST0, 0x0D050B03);
mmio_write_32(DBSC_SCFCTST1, 0x0306030C);
mmio_write_32(DBSC_DBPDLK_0, 0x0000A55A);
mmio_write_32(DBSC_DBCMD, 0x01000001);
@ -426,13 +453,14 @@ static void init_ddr_d3_1600(void)
;
mmio_write_32(DBSC_DBPDRGA_0, 0x00000004);
mmio_write_32(DBSC_DBPDRGD_0, 0x08C05FF0);
mmio_write_32(DBSC_DBPDRGD_0,
(uint32_t) (REFRESH_RATE * 792 / 125) - 400 + 0x08B00000);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000022);
mmio_write_32(DBSC_DBPDRGD_0, 0x1000040B);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000023);
mmio_write_32(DBSC_DBPDRGD_0, 0x2D9C0B66);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000024);
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88C400);
mmio_write_32(DBSC_DBPDRGD_0, 0x2A88B400);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000025);
mmio_write_32(DBSC_DBPDRGD_0, 0x30005200);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000026);
@ -442,7 +470,11 @@ static void init_ddr_d3_1600(void)
mmio_write_32(DBSC_DBPDRGA_0, 0x00000028);
mmio_write_32(DBSC_DBPDRGD_0, 0x00000046);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000029);
mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
if (REFRESH_RATE > 3900) {
mmio_write_32(DBSC_DBPDRGD_0, 0x00000018);
} else {
mmio_write_32(DBSC_DBPDRGD_0, 0x00000098);
}
mmio_write_32(DBSC_DBPDRGA_0, 0x0000002C);
mmio_write_32(DBSC_DBPDRGD_0, 0x81003047);
mmio_write_32(DBSC_DBPDRGA_0, 0x00000020);
@ -549,9 +581,11 @@ static void init_ddr_d3_1600(void)
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
r2 = mmio_read_32(DBSC_DBPDRGD_0);
mmio_write_32(DBSC_DBPDRGA_0, 0x000000AF);
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
r2 = mmio_read_32(DBSC_DBPDRGD_0);
mmio_write_32(DBSC_DBPDRGA_0, 0x000000CF);
mmio_write_32(DBSC_DBPDRGD_0, ((r2 + 0x1) & 0xFF) | (r2 & 0xFFFFFF00));
mmio_write_32(DBSC_DBPDRGA_0, 0x000000A0);
@ -620,8 +654,10 @@ static void init_ddr_d3_1600(void)
mmio_write_32(DBSC_DBPDRGD_0, 0x0024643E);
mmio_write_32(DBSC_DBBUS0CNF1, 0x00000010);
mmio_write_32(DBSC_DBCALCNF, 0x0100401B);
mmio_write_32(DBSC_DBRFCNF1, 0x00080C30);
mmio_write_32(DBSC_DBCALCNF,
(uint32_t) (64000000 / REFRESH_RATE) + 0x01000000);
mmio_write_32(DBSC_DBRFCNF1,
(uint32_t) (REFRESH_RATE * 99 / 125) + 0x00080000);
mmio_write_32(DBSC_DBRFCNF2, 0x00010000);
mmio_write_32(DBSC_DBDFICUPDCNF, 0x40100001);
mmio_write_32(DBSC_DBRFEN, 0x00000001);
@ -693,7 +729,7 @@ int32_t rcar_dram_init(void)
ddr_mbps = 1600;
}
NOTICE("BL2: DDR%d\n", ddr_mbps);
NOTICE("BL2: DDR%d(%s)\n", ddr_mbps, RCAR_DDR_VERSION);
return 0;
}

6
drivers/renesas/common/io/io_rcar.c
View File

@ -151,6 +151,9 @@ int32_t rcar_get_certificate(const int32_t name, uint32_t *cert)
return -EINVAL;
}
#define MFISBTSTSR (0xE6260604U)
#define MFISBTSTSR_BOOT_PARTITION (0x00000010U)
static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
uint32_t *cert, uint32_t *no_load,
uintptr_t *partition)
@ -169,6 +172,9 @@ static int32_t file_to_offset(const int32_t name, uintptr_t *offset,
}
*offset = rcar_image_header[addr];
if (mmio_read_32(MFISBTSTSR) & MFISBTSTSR_BOOT_PARTITION)
*offset += 0x800000;
*cert = RCAR_CERT_SIZE;
*cert *= RCAR_ATTR_GET_CERTOFF(name_offset[i].attr);
*cert += RCAR_SDRAM_certESS;

24
drivers/renesas/common/pwrc/pwrc.c
View File

@ -44,6 +44,7 @@ RCAR_INSTANTIATE_LOCK
#define CPU_PWR_OFF (0x00000003U)
#define RCAR_PSTR_MASK (0x00000003U)
#define ST_ALL_STANDBY (0x00003333U)
#define SYSCEXTMASK_EXTMSK0 (0x00000001U)
/* Suspend to ram */
#define DBSC4_REG_BASE (0xE6790000U)
#define DBSC4_REG_DBSYSCNT0 (DBSC4_REG_BASE + 0x0100U)
@ -191,6 +192,8 @@ static void scu_power_up(uint64_t mpidr)
{
uintptr_t reg_pwrsr, reg_cpumcr, reg_pwron, reg_pwrer;
uint32_t c, sysc_reg_bit;
uint32_t lsi_product;
uint32_t lsi_cut;
c = rcar_pwrc_get_mpidr_cluster(mpidr);
reg_cpumcr = IS_CA57(c) ? RCAR_CA57CPUCMCR : RCAR_CA53CPUCMCR;
@ -205,6 +208,17 @@ static void scu_power_up(uint64_t mpidr)
if (mmio_read_32(reg_cpumcr) != 0)
mmio_write_32(reg_cpumcr, 0);
lsi_product = mmio_read_32((uintptr_t)RCAR_PRR);
lsi_cut = lsi_product & PRR_CUT_MASK;
lsi_product &= PRR_PRODUCT_MASK;
if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
lsi_product == PRR_PRODUCT_H3 ||
lsi_product == PRR_PRODUCT_M3N ||
lsi_product == PRR_PRODUCT_E3) {
mmio_setbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
}
mmio_setbits_32(RCAR_SYSCIER, sysc_reg_bit);
mmio_setbits_32(RCAR_SYSCIMR, sysc_reg_bit);
@ -216,7 +230,15 @@ static void scu_power_up(uint64_t mpidr)
while ((mmio_read_32(RCAR_SYSCISR) & sysc_reg_bit) == 0)
;
mmio_write_32(RCAR_SYSCISR, sysc_reg_bit);
mmio_write_32(RCAR_SYSCISCR, sysc_reg_bit);
if ((lsi_product == PRR_PRODUCT_M3 && lsi_cut >= PRR_PRODUCT_30) ||
lsi_product == PRR_PRODUCT_H3 ||
lsi_product == PRR_PRODUCT_M3N ||
lsi_product == PRR_PRODUCT_E3) {
mmio_clrbits_32(RCAR_SYSCEXTMASK, SYSCEXTMASK_EXTMSK0);
}
while ((mmio_read_32(reg_pwrsr) & STATUS_PWRUP) == 0)
;
}

26
drivers/renesas/common/scif/scif.S
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -79,7 +79,7 @@
SCSMR_STOP_1 + \
SCSMR_CKS_DIV1)
#define SCBRR_115200BPS (17)
#define SCBRR_115200BPSON (16)
#define SCBRR_115200BPS_D3_SSCG (16)
#define SCBRR_115200BPS_E3_SSCG (15)
#define SCBRR_230400BPS (8)
@ -216,26 +216,38 @@ func console_rcar_init
and w1, w1, #PRR_PRODUCT_MASK
mov w2, #PRR_PRODUCT_D3
cmp w1, w2
beq 4f
beq 5f
and w1, w1, #PRR_PRODUCT_MASK
mov w2, #PRR_PRODUCT_E3
cmp w1, w2
bne 5f
bne 4f
/* When SSCG(MD12) on (E3) */
ldr x1, =RST_MODEMR
ldr w1, [x1]
and w1, w1, #MODEMR_MD12
mov w2, #MODEMR_MD12
cmp w1, w2
bne 5f
bne 4f
/* When SSCG(MD12) on (E3) */
mov w1, #SCBRR_115200BPS_E3_SSCG
b 2f
5:
mov w1, #SCBRR_115200BPS
/* In case of D3 */
ldr x1, =RST_MODEMR
ldr w1, [x1]
and w1, w1, #MODEMR_MD12
mov w2, #MODEMR_MD12
cmp w1, w2
bne 4f
/* When SSCG(MD12) on (D3) */
mov w1, #SCBRR_115200BPS_D3_SSCG
b 2f
4:
mov w1, #SCBRR_115200BPSON
/* In case of H3/M3/M3N or when SSCG(MD12) is off in E3/D3 */
mov w1, #SCBRR_115200BPS
b 2f
3:
mov w1, #SCBRR_230400BPS

6
drivers/renesas/common/watchdog/swdt.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -78,7 +78,7 @@ static void swdt_disable(void)
void rcar_swdt_init(void)
{
uint32_t rmsk, sr;
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RZ_G2E)
#if (RCAR_LSI != RCAR_E3) && (RCAR_LSI != RCAR_D3) && (RCAR_LSI != RZ_G2E)
uint32_t reg, val, product_cut, chk_data;
reg = mmio_read_32(RCAR_PRR);
@ -96,6 +96,8 @@ void rcar_swdt_init(void)
#if (RCAR_LSI == RCAR_E3) || (RCAR_LSI == RZ_G2E)
mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_7p81k);
#elif (RCAR_LSI == RCAR_D3)
mmio_write_32(SWDT_WTCNT, WTCNT_UPPER_BYTE | WTCNT_COUNT_8p13k);
#else
val = WTCNT_UPPER_BYTE;

6
plat/renesas/common/aarch64/plat_helpers.S
View File

@ -1,6 +1,6 @@
/*
* Copyright (c) 2013-2020, ARM Limited and Contributors. All rights reserved.
* Copyright (c) 2015-2019, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -284,7 +284,11 @@ func plat_crash_console_putc
str x3, [sp, #-16]!
str x4, [sp, #-16]!
str x5, [sp, #-16]!
str x6, [sp, #-16]!
str x7, [sp, #-16]!
bl console_rcar_putc
ldr x7, [sp], #16
ldr x6, [sp], #16
ldr x5, [sp], #16
ldr x4, [sp], #16
ldr x3, [sp], #16

34
plat/renesas/common/bl2_cpg_init.c
View File

@ -40,7 +40,6 @@ static void bl2_system_cpg_init_e3(void);
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
static void bl2_realtime_cpg_init_d3(void);
static void bl2_system_cpg_init_d3(void);
#endif
@ -140,7 +139,7 @@ static void bl2_system_cpg_init_h3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x80000004U);
cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -176,7 +175,7 @@ static void bl2_system_cpg_init_m3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x80000004U);
cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -212,7 +211,7 @@ static void bl2_system_cpg_init_m3n(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x040E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x80000004U);
cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -246,7 +245,7 @@ static void bl2_system_cpg_init_v3m(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x340E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x80000004U);
cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -280,7 +279,7 @@ static void bl2_system_cpg_init_e3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x000E2FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x80000004U);
cpg_write(SMSTPCR4, 0x80000000U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0xC3FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -292,23 +291,6 @@ static void bl2_system_cpg_init_e3(void)
#endif
#if (RCAR_LSI == RCAR_AUTO) || (RCAR_LSI == RCAR_D3)
static void bl2_realtime_cpg_init_d3(void)
{
/* Realtime Module Stop Control Registers */
cpg_write(RMSTPCR0, 0x00010000U);
cpg_write(RMSTPCR1, 0xFFFFFFFFU);
cpg_write(RMSTPCR2, 0x00060FDCU);
cpg_write(RMSTPCR3, 0xFFFFFFDFU);
cpg_write(RMSTPCR4, 0x80000184U);
cpg_write(RMSTPCR5, 0x83FFFFFFU);
cpg_write(RMSTPCR6, 0xFFFFFFFFU);
cpg_write(RMSTPCR7, 0xFFFFFFFFU);
cpg_write(RMSTPCR8, 0x00F1FFF7U);
cpg_write(RMSTPCR9, 0xF3F5E016U);
cpg_write(RMSTPCR10, 0xFFFEFFE0U);
cpg_write(RMSTPCR11, 0x000000B7U);
}
static void bl2_system_cpg_init_d3(void)
{
/* System Module Stop Control Registers */
@ -316,7 +298,7 @@ static void bl2_system_cpg_init_d3(void)
cpg_write(SMSTPCR1, 0xFFFFFFFFU);
cpg_write(SMSTPCR2, 0x00060FDCU);
cpg_write(SMSTPCR3, 0xFFFFFBDFU);
cpg_write(SMSTPCR4, 0x00000084U);
cpg_write(SMSTPCR4, 0x00000080U | (mmio_read_32(SMSTPCR4) & 0x4));
cpg_write(SMSTPCR5, 0x83FFFFFFU);
cpg_write(SMSTPCR6, 0xFFFFFFFFU);
cpg_write(SMSTPCR7, 0xFFFFFFFFU);
@ -356,7 +338,7 @@ void bl2_cpg_init(void)
bl2_realtime_cpg_init_e3();
break;
case PRR_PRODUCT_D3:
bl2_realtime_cpg_init_d3();
/* no need */
break;
default:
panic();
@ -373,7 +355,7 @@ void bl2_cpg_init(void)
#elif RCAR_LSI == RCAR_E3 || RCAR_LSI == RZ_G2E
bl2_realtime_cpg_init_e3();
#elif RCAR_LSI == RCAR_D3
bl2_realtime_cpg_init_d3();
/* no need */
#else
#error "Don't have CPG initialize routine(unknown)."
#endif

12
plat/renesas/common/bl2_secure_setting.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -49,10 +49,10 @@ static const struct {
/*
* Bit13: SCEG PKA (secure APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* 1: Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* 0: registers accessed from secure resource only
* 1: Reserved[R-Car E3]
* 1: Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* 0: registers accessed from secure resource only
*/
@ -152,14 +152,14 @@ static const struct {
* Security group 1 attribute setting for slave ports 6
* Bit13: SCEG PKA (secure APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Reserved[R-Car E3/D3]
* Bit12: SCEG PKA (public APB) slave ports
* SecurityGroup3
* Reserved[R-Car E3]
* Reserved[R-Car E3/D3]
* Bit10: SCEG Secure Core slave ports
* SecurityGroup3
*/
#if RCAR_LSI == RCAR_E3
#if RCAR_LSI == RCAR_E3 || RCAR_LSI == RCAR_D3
{ SEC_GRP0COND6, 0x00000400U },
{ SEC_GRP1COND6, 0x00000400U },
#else /* RCAR_LSI == RCAR_E3 */

9
plat/renesas/common/common.mk
View File

@ -1,5 +1,5 @@
#
# Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
# Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
#
# SPDX-License-Identifier: BSD-3-Clause
#
@ -65,10 +65,12 @@ $(eval $(call add_define,RCAR_CUT_30))
ERRATA_A53_835769 := 1
ERRATA_A53_843419 := 1
ERRATA_A53_855873 := 1
ERRATA_A53_1530924 := 1
# Enable workarounds for selected Cortex-A57 erratas.
ERRATA_A57_859972 := 1
ERRATA_A57_813419 := 1
ERRATA_A57_1319537 := 1
PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
-Iplat/renesas/common/include \
@ -77,9 +79,8 @@ PLAT_INCLUDES := -Iplat/renesas/common/include/registers \
PLAT_BL_COMMON_SOURCES := drivers/renesas/common/iic_dvfs/iic_dvfs.c \
plat/renesas/common/rcar_common.c
RCAR_GIC_SOURCES := drivers/arm/gic/common/gic_common.c \
drivers/arm/gic/v2/gicv2_main.c \
drivers/arm/gic/v2/gicv2_helpers.c \
include drivers/arm/gic/v2/gicv2.mk
RCAR_GIC_SOURCES := ${GICV2_SOURCES} \
plat/common/plat_gicv2.c
BL2_SOURCES += ${RCAR_GIC_SOURCES} \

4
plat/renesas/common/include/platform_def.h
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -144,7 +144,7 @@
******************************************************************************/
#ifndef SPD_NONE
#define BL32_BASE U(0x44100000)
#define BL32_LIMIT (BL32_BASE + U(0x100000))
#define BL32_LIMIT (BL32_BASE + U(0x200000))
#endif
/*******************************************************************************

4
plat/renesas/common/include/rcar_def.h
View File

@ -148,9 +148,13 @@
#define RCAR_PWRER5 U(0xE61801D4) /* shutoff/resume error */
#define RCAR_SYSCISR U(0xE6180004) /* Interrupt status */
#define RCAR_SYSCISCR U(0xE6180008) /* Interrupt stat clear */
#define RCAR_SYSCEXTMASK U(0xE61802F8) /* External Request Mask */
/* H3/H3-N, M3 v3.0, M3-N, E3 */
/* Product register */
#define RCAR_PRR U(0xFFF00044)
#define RCAR_M3_CUT_VER11 U(0x00000010) /* M3 Ver.1.1/Ver.1.2 */
#define RCAR_D3_CUT_VER10 U(0x00000000) /* D3 Ver.1.0 */
#define RCAR_D3_CUT_VER11 U(0x00000010) /* D3 Ver.1.1 */
#define RCAR_MAJOR_MASK U(0x000000F0)
#define RCAR_MINOR_MASK U(0x0000000F)
#define PRR_PRODUCT_SHIFT U(8)

38
plat/renesas/rcar/bl2_plat_setup.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2018-2020, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2018-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -263,9 +263,6 @@ void bl2_plat_flush_bl31_params(void)
if (product == PRR_PRODUCT_H3 && PRR_PRODUCT_20 > cut)
goto tlb;
if (product == PRR_PRODUCT_D3)
goto tlb;
/* Disable MFIS write protection */
mmio_write_32(MFISWPCNTR, MFISWPCNTR_PASSWORD | 1);
@ -708,6 +705,7 @@ static void bl2_advertise_dram_size(uint32_t product)
[4] = 0x600000000ULL,
[6] = 0x700000000ULL,
};
uint32_t cut = mmio_read_32(RCAR_PRR) & PRR_CUT_MASK;
switch (product) {
case PRR_PRODUCT_H3:
@ -733,15 +731,21 @@ static void bl2_advertise_dram_size(uint32_t product)
break;
case PRR_PRODUCT_M3:
if (cut < PRR_PRODUCT_30) {
#if (RCAR_GEN3_ULCB == 1)
/* 2GB(1GBx2 2ch split) */
dram_config[1] = 0x40000000ULL;
dram_config[5] = 0x40000000ULL;
/* 2GB(1GBx2 2ch split) */
dram_config[1] = 0x40000000ULL;
dram_config[5] = 0x40000000ULL;
#else
/* 4GB(2GBx2 2ch split) */
dram_config[1] = 0x80000000ULL;
dram_config[5] = 0x80000000ULL;
/* 4GB(2GBx2 2ch split) */
dram_config[1] = 0x80000000ULL;
dram_config[5] = 0x80000000ULL;
#endif
} else {
/* 8GB(2GBx4 2ch split) */
dram_config[1] = 0x100000000ULL;
dram_config[5] = 0x100000000ULL;
}
break;
case PRR_PRODUCT_M3N:
@ -897,6 +901,14 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
str,
(reg & RCAR_MINOR_MASK) + RCAR_M3_MINOR_OFFSET);
}
} else if (product == PRR_PRODUCT_D3) {
if (RCAR_D3_CUT_VER10 == (reg & PRR_CUT_MASK)) {
NOTICE("BL2: PRR is R-Car %s Ver.1.0\n", str);
} else if (RCAR_D3_CUT_VER11 == (reg & PRR_CUT_MASK)) {
NOTICE("BL2: PRR is R-Car %s Ver.1.1\n", str);
} else {
NOTICE("BL2: PRR is R-Car %s Ver.X.X\n", str);
}
} else {
major = (reg & RCAR_MAJOR_MASK) >> RCAR_MAJOR_SHIFT;
major = major + RCAR_MAJOR_OFFSET;
@ -904,7 +916,7 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
NOTICE("BL2: PRR is R-Car %s Ver.%d.%d\n", str, major, minor);
}
if (product == PRR_PRODUCT_E3) {
if (PRR_PRODUCT_E3 == product || PRR_PRODUCT_D3 == product) {
reg = mmio_read_32(RCAR_MODEMR);
sscg = reg & RCAR_SSCG_MASK;
str = sscg == RCAR_SSCG_ENABLE ? sscg_on : sscg_off;
@ -968,10 +980,6 @@ void bl2_el3_early_platform_setup(u_register_t arg1, u_register_t arg2,
str = boot_emmc25x1;
break;
case MODEMR_BOOT_DEV_EMMC_50X8:
#if RCAR_LSI == RCAR_D3
ERROR("BL2: Failed to Initialize. eMMC is not supported.\n");
panic();
#endif
str = boot_emmc50x8;
break;
default:

4
tools/renesas/rcar_layout_create/sa6.c
View File

@ -1,5 +1,5 @@
/*
* Copyright (c) 2015-2017, Renesas Electronics Corporation. All rights reserved.
* Copyright (c) 2015-2021, Renesas Electronics Corporation. All rights reserved.
*
* SPDX-License-Identifier: BSD-3-Clause
*/
@ -96,7 +96,7 @@
#define RCAR_BL32DST_ADDRESS (0x44100000U)
#define RCAR_BL32DST_ADDRESSH (0x00000000U)
/* Destination size for BL32 */
#define RCAR_BL32DST_SIZE (0x00040000U)
#define RCAR_BL32DST_SIZE (0x00080000U)
/* Destination address for BL33 */
#define RCAR_BL33DST_ADDRESS (0x50000000U)
#define RCAR_BL33DST_ADDRESSH (0x00000000U)