Merge pull request #1097 from davidcunado-arm/dc/reset_bl31
plat/arm: Fix BL31_BASE when RESET_TO_BL31=1
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commit
a747b08e3a
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@ -1593,15 +1593,15 @@ with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
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-C cluster0.NUM_CORES=4 \
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-C cluster0.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cluster1.NUM_CORES=4 \
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-C cache_state_modelled=1 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBAR=0x04023000 \
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-C cluster0.cpu0.RVBAR=0x04020000 \
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-C cluster0.cpu1.RVBAR=0x04023000 \
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-C cluster0.cpu1.RVBAR=0x04020000 \
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-C cluster0.cpu2.RVBAR=0x04023000 \
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-C cluster0.cpu2.RVBAR=0x04020000 \
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-C cluster0.cpu3.RVBAR=0x04023000 \
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-C cluster0.cpu3.RVBAR=0x04020000 \
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-C cluster1.cpu0.RVBAR=0x04023000 \
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-C cluster1.cpu0.RVBAR=0x04020000 \
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-C cluster1.cpu1.RVBAR=0x04023000 \
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-C cluster1.cpu1.RVBAR=0x04020000 \
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-C cluster1.cpu2.RVBAR=0x04023000 \
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-C cluster1.cpu2.RVBAR=0x04020000 \
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-C cluster1.cpu3.RVBAR=0x04023000 \
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-C cluster1.cpu3.RVBAR=0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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@ -1678,15 +1678,15 @@ boot Linux with 8 CPUs using the AArch64 build of ARM Trusted Firmware.
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-C bp.secure_memory=1 \
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-C bp.secure_memory=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C bp.tzc_400.diagnostics=1 \
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-C cache_state_modelled=1 \
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-C cache_state_modelled=1 \
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-C cluster0.cpu0.RVBARADDR=0x04023000 \
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-C cluster0.cpu0.RVBARADDR=0x04020000 \
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-C cluster0.cpu1.RVBARADDR=0x04023000 \
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-C cluster0.cpu1.RVBARADDR=0x04020000 \
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-C cluster0.cpu2.RVBARADDR=0x04023000 \
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-C cluster0.cpu2.RVBARADDR=0x04020000 \
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-C cluster0.cpu3.RVBARADDR=0x04023000 \
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-C cluster0.cpu3.RVBARADDR=0x04020000 \
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-C cluster1.cpu0.RVBARADDR=0x04023000 \
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-C cluster1.cpu0.RVBARADDR=0x04020000 \
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-C cluster1.cpu1.RVBARADDR=0x04023000 \
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-C cluster1.cpu1.RVBARADDR=0x04020000 \
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-C cluster1.cpu2.RVBARADDR=0x04023000 \
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-C cluster1.cpu2.RVBARADDR=0x04020000 \
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-C cluster1.cpu3.RVBARADDR=0x04023000 \
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-C cluster1.cpu3.RVBARADDR=0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04023000 \
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--data cluster0.cpu0="<path-to>/<bl31-binary>"@0x04020000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl32-binary>"@0x04001000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<bl33-binary>"@0x88000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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--data cluster0.cpu0="<path-to>/<fdt>"@0x82000000 \
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@ -292,6 +292,13 @@
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#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
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#define BL31_BASE ARM_AP_TZC_DRAM1_BASE
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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#define BL31_LIMIT (ARM_AP_TZC_DRAM1_BASE + \
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PLAT_ARM_MAX_BL31_SIZE)
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PLAT_ARM_MAX_BL31_SIZE)
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#elif (RESET_TO_BL31)
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/*
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* Put BL31_BASE in the middle of the Trusted SRAM.
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*/
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#define BL31_BASE (ARM_TRUSTED_SRAM_BASE + \
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(PLAT_ARM_TRUSTED_SRAM_SIZE >> 1))
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#define BL31_LIMIT (ARM_BL_RAM_BASE + ARM_BL_RAM_SIZE)
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#else
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#else
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/*
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/*
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* Put BL31 at the top of the Trusted SRAM.
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* Put BL31 at the top of the Trusted SRAM.
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