Tegra: per-soc `get_target_pwr_state` handler
This patch implements a per-soc handler to calculate the target power state for the cluster/system. A weak implementation of the handler is provided for platforms to use by default. For SoCs with multiple CPU clusters, this handler would provide the individual cluster/system state, allowing the PSCI service to flush caches during cluster/system power down. Change-Id: I568cdb42204f9841a8430bd9105bd694f71cf91d Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -57,6 +57,7 @@ extern uint64_t tegra_sec_entry_point;
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#pragma weak tegra_soc_pwr_domain_power_down_wfi
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#pragma weak tegra_soc_pwr_domain_power_down_wfi
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#pragma weak tegra_soc_prepare_system_reset
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#pragma weak tegra_soc_prepare_system_reset
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#pragma weak tegra_soc_prepare_system_off
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#pragma weak tegra_soc_prepare_system_off
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#pragma weak tegra_soc_get_target_pwr_state
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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int tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
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{
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{
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@ -94,6 +95,23 @@ __dead2 void tegra_soc_prepare_system_off(void)
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panic();
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panic();
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}
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}
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plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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unsigned int ncpu)
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{
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plat_local_state_t target = PLAT_MAX_RET_STATE, temp;
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assert(ncpu);
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do {
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temp = *states++;
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if ((temp > target) && (temp != PLAT_MAX_OFF_STATE))
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target = temp;
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} while (--ncpu);
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return target;
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}
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/*******************************************************************************
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/*******************************************************************************
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* This handler is called by the PSCI implementation during the `SYSTEM_SUSPEND`
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* call to get the `power_state` parameter. This allows the platform to encode
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* call to get the `power_state` parameter. This allows the platform to encode
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@ -102,12 +120,9 @@ __dead2 void tegra_soc_prepare_system_off(void)
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******************************************************************************/
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******************************************************************************/
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void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
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void tegra_get_sys_suspend_power_state(psci_power_state_t *req_state)
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{
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{
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/* lower affinities use PLAT_MAX_OFF_STATE */
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/* all affinities use system suspend state id */
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for (int i = MPIDR_AFFLVL0; i < PLAT_MAX_PWR_LVL; i++)
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for (int i = MPIDR_AFFLVL0; i <= PLAT_MAX_PWR_LVL; i++)
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req_state->pwr_domain_state[i] = PLAT_MAX_OFF_STATE;
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req_state->pwr_domain_state[i] = PSTATE_ID_SOC_POWERDN;
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/* max affinity uses system suspend state id */
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req_state->pwr_domain_state[PLAT_MAX_PWR_LVL] = PSTATE_ID_SOC_POWERDN;
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -333,15 +348,5 @@ plat_local_state_t plat_get_target_pwr_state(unsigned int lvl,
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const plat_local_state_t *states,
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const plat_local_state_t *states,
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unsigned int ncpu)
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unsigned int ncpu)
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{
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{
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plat_local_state_t target = PLAT_MAX_RET_STATE, temp;
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return tegra_soc_get_target_pwr_state(lvl, states, ncpu);
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assert(ncpu);
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do {
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temp = *states++;
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if ((temp > target) && (temp != PLAT_MAX_OFF_STATE))
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target = temp;
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} while (--ncpu);
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return target;
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}
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}
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