Aarch64: Add support for FEAT_PANx extensions
This patch provides the changes listed below: - Adds new bit fields definitions for SCTLR_EL1/2 registers - Corrects the name of SCTLR_EL1/2.[20] bit field from SCTLR_UWXN_BIT to SCTLR_TSCXT_BIT - Adds FEAT_PANx bit field definitions and their possible values for ID_AA64MMFR1_EL1 register. - Adds setting of SCTLR_EL1.SPAN bit to preserve PSTATE.PAN on taking an exception to EL1 in spm_sp_setup() function (services\std_svc\spm_mm\spm_mm_setup.c) Change-Id: If51f20e7995c649126a7728a4d0867041fdade19 Signed-off-by: Alexei Fedorov <Alexei.Fedorov@arm.com>
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Alexei Fedorov
parent
20c378920e
commit
a83103c824
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@ -243,6 +243,13 @@
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#define ID_AA64MMFR1_EL1_TWED_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR1_EL1_TWED_NOT_SUPPORTED ULL(0x0)
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#define ID_AA64MMFR1_EL1_PAN_SHIFT U(20)
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#define ID_AA64MMFR1_EL1_PAN_MASK ULL(0xf)
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#define ID_AA64MMFR1_EL1_PAN_NOT_SUPPORTED ULL(0x0)
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#define ID_AA64MMFR1_EL1_PAN_SUPPORTED ULL(0x1)
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#define ID_AA64MMFR1_EL1_PAN2_SUPPORTED ULL(0x2)
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#define ID_AA64MMFR1_EL1_PAN3_SUPPORTED ULL(0x3)
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/* ID_AA64MMFR2_EL1 definitions */
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#define ID_AA64MMFR2_EL1 S3_0_C0_C7_2
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@ -286,6 +293,7 @@
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#define SCTLR_EL1_RES1 ((UL(1) << 29) | (UL(1) << 28) | (UL(1) << 23) | \
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(UL(1) << 22) | (UL(1) << 20) | (UL(1) << 11))
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#define SCTLR_AARCH32_EL1_RES1 \
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((U(1) << 23) | (U(1) << 22) | (U(1) << 11) | \
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(U(1) << 4) | (U(1) << 3))
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@ -300,9 +308,12 @@
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#define SCTLR_SA_BIT (ULL(1) << 3)
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#define SCTLR_SA0_BIT (ULL(1) << 4)
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#define SCTLR_CP15BEN_BIT (ULL(1) << 5)
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#define SCTLR_nAA_BIT (ULL(1) << 6)
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#define SCTLR_ITD_BIT (ULL(1) << 7)
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#define SCTLR_SED_BIT (ULL(1) << 8)
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#define SCTLR_UMA_BIT (ULL(1) << 9)
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#define SCTLR_EnRCTX_BIT (ULL(1) << 10)
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#define SCTLR_EOS_BIT (ULL(1) << 11)
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#define SCTLR_I_BIT (ULL(1) << 12)
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#define SCTLR_EnDB_BIT (ULL(1) << 13)
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#define SCTLR_DZE_BIT (ULL(1) << 14)
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@ -310,21 +321,65 @@
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#define SCTLR_NTWI_BIT (ULL(1) << 16)
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#define SCTLR_NTWE_BIT (ULL(1) << 18)
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#define SCTLR_WXN_BIT (ULL(1) << 19)
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#define SCTLR_UWXN_BIT (ULL(1) << 20)
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#define SCTLR_TSCXT_BIT (ULL(1) << 20)
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#define SCTLR_IESB_BIT (ULL(1) << 21)
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#define SCTLR_EIS_BIT (ULL(1) << 22)
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#define SCTLR_SPAN_BIT (ULL(1) << 23)
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#define SCTLR_E0E_BIT (ULL(1) << 24)
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#define SCTLR_EE_BIT (ULL(1) << 25)
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#define SCTLR_UCI_BIT (ULL(1) << 26)
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#define SCTLR_EnDA_BIT (ULL(1) << 27)
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#define SCTLR_nTLSMD_BIT (ULL(1) << 28)
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#define SCTLR_LSMAOE_BIT (ULL(1) << 29)
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#define SCTLR_EnIB_BIT (ULL(1) << 30)
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#define SCTLR_EnIA_BIT (ULL(1) << 31)
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#define SCTLR_BT0_BIT (ULL(1) << 35)
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#define SCTLR_BT1_BIT (ULL(1) << 36)
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#define SCTLR_BT_BIT (ULL(1) << 36)
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#define SCTLR_ITFSB_BIT (ULL(1) << 37)
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#define SCTLR_TCF0_SHIFT U(38)
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#define SCTLR_TCF0_MASK ULL(3)
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/* Tag Check Faults in EL0 have no effect on the PE */
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#define SCTLR_TCF0_NO_EFFECT U(0)
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/* Tag Check Faults in EL0 cause a synchronous exception */
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#define SCTLR_TCF0_SYNC U(1)
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/* Tag Check Faults in EL0 are asynchronously accumulated */
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#define SCTLR_TCF0_ASYNC U(2)
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/*
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* Tag Check Faults in EL0 cause a synchronous exception on reads,
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* and are asynchronously accumulated on writes
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*/
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#define SCTLR_TCF0_SYNCR_ASYNCW U(3)
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#define SCTLR_TCF_SHIFT U(40)
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#define SCTLR_TCF_MASK ULL(3)
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/* Tag Check Faults in EL1 have no effect on the PE */
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#define SCTLR_TCF_NO_EFFECT U(0)
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/* Tag Check Faults in EL1 cause a synchronous exception */
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#define SCTLR_TCF_SYNC U(1)
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/* Tag Check Faults in EL1 are asynchronously accumulated */
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#define SCTLR_TCF_ASYNC U(2)
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/*
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* Tag Check Faults in EL1 cause a synchronous exception on reads,
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* and are asynchronously accumulated on writes
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*/
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#define SCTLR_TCF_SYNCR_ASYNCW U(3)
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#define SCTLR_ATA0_BIT (ULL(1) << 42)
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#define SCTLR_ATA_BIT (ULL(1) << 43)
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#define SCTLR_DSSBS_BIT (ULL(1) << 44)
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#define SCTLR_TWEDEn_BIT (ULL(1) << 45)
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#define SCTLR_TWEDEL_SHIFT U(46)
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#define SCTLR_TWEDEL_MASK ULL(0xf)
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#define SCTLR_EnASR_BIT (ULL(1) << 54)
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#define SCTLR_EnAS0_BIT (ULL(1) << 55)
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#define SCTLR_EnALS_BIT (ULL(1) << 56)
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#define SCTLR_EPAN_BIT (ULL(1) << 57)
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#define SCTLR_RESET_VAL SCTLR_EL3_RES1
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/* CPACR_El1 definitions */
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/* CPACR_EL1 definitions */
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#define CPACR_EL1_FPEN(x) ((x) << 20)
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#define CPACR_EL1_FP_TRAP_EL0 UL(0x1)
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#define CPACR_EL1_FP_TRAP_ALL UL(0x2)
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@ -1,5 +1,5 @@
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/*
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* Copyright (c) 2017-2019, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2017-2020, ARM Limited and Contributors. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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@ -142,6 +142,8 @@ void spm_sp_setup(sp_context_t *sp_ctx)
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SCTLR_DZE_BIT |
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/* Enable SP Alignment check for EL0 */
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SCTLR_SA0_BIT |
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/* Don't change PSTATE.PAN on taking an exception to EL1 */
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SCTLR_SPAN_BIT |
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/* Allow cacheable data and instr. accesses to normal memory. */
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SCTLR_C_BIT | SCTLR_I_BIT |
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/* Enable MMU. */
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