Merge changes I9c9ed516,I2788eaf6 into integration
* changes: qemu/qemu_sbsa: fix memory type of secure NOR flash qemu/qemu_sbsa: spm_mm supports 512 cores
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commit
a8fb76e59c
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@ -29,20 +29,8 @@ mmap_region_t plat_qemu_secure_partition_mmap[] = {
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{0}
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};
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/*
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* Boot information passed to a secure partition during initialisation.
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* Linear indices in MP information will be filled at runtime.
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*/
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static spm_mm_mp_info_t sp_mp_info[] = {
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[0] = {0x80000000, 0},
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[1] = {0x80000001, 0},
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[2] = {0x80000002, 0},
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[3] = {0x80000003, 0},
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[4] = {0x80000004, 0},
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[5] = {0x80000005, 0},
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[6] = {0x80000006, 0},
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[7] = {0x80000007, 0}
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};
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/* Boot information passed to a secure partition during initialisation. */
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static spm_mm_mp_info_t sp_mp_info[PLATFORM_CORE_COUNT];
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spm_mm_boot_info_t plat_qemu_secure_partition_boot_info = {
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.h.type = PARAM_SP_IMAGE_BOOT_INFO,
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@ -71,6 +59,25 @@ ehf_pri_desc_t qemu_exceptions[] = {
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EHF_PRI_DESC(QEMU_PRI_BITS, PLAT_SP_PRI)
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};
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static void qemu_initialize_mp_info(spm_mm_mp_info_t *mp_info)
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{
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unsigned int i, j;
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spm_mm_mp_info_t *tmp = mp_info;
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for (i = 0; i < PLATFORM_CLUSTER_COUNT; i++) {
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for (j = 0; j < PLATFORM_MAX_CPUS_PER_CLUSTER; j++) {
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tmp->mpidr = (0x80000000 | (i << MPIDR_AFF1_SHIFT)) + j;
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/*
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* Linear indices and flags will be filled
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* in the spm_mm service.
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*/
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tmp->linear_id = 0;
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tmp->flags = 0;
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tmp++;
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}
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}
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}
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int dt_add_ns_buf_node(uintptr_t *base)
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{
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uintptr_t addr;
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@ -134,5 +141,7 @@ const mmap_region_t *plat_get_secure_partition_mmap(void *cookie)
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const spm_mm_boot_info_t *
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plat_get_secure_partition_boot_info(void *cookie)
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{
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qemu_initialize_mp_info(sp_mp_info);
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return &plat_qemu_secure_partition_boot_info;
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}
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@ -171,7 +171,7 @@
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#if SPM_MM && defined(IMAGE_BL31)
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# define PLAT_SP_IMAGE_MMAP_REGIONS 30
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 20
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# define PLAT_SP_IMAGE_MAX_XLAT_TABLES 50
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#endif
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/*
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@ -353,7 +353,7 @@
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#define MAP_SECURE_VARSTORE MAP_REGION_FLAT( \
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QEMU_SECURE_VARSTORE_BASE, \
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QEMU_SECURE_VARSTORE_SIZE, \
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MT_MEMORY | MT_RW | \
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MT_DEVICE | MT_RW | \
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MT_SECURE | MT_USER)
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#endif
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