Merge "meson: gxl: Fix reset and power off" into integration
This commit is contained in:
commit
a91e904324
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -10,6 +10,7 @@
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#include <common/interrupt_props.h>
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#include <common/interrupt_props.h>
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#include <plat/common/platform.h>
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#include <plat/common/platform.h>
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#include <platform_def.h>
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#include <platform_def.h>
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#include <lib/mmio.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include <lib/xlat_tables/xlat_mmu_helpers.h>
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#include "gxl_private.h"
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#include "gxl_private.h"
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@ -100,12 +101,19 @@ void bl31_plat_arch_setup(void)
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enable_mmu_el3(0);
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enable_mmu_el3(0);
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}
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}
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static inline bool gxl_scp_ready(void)
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{
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return GXBB_AO_RTI_SCP_IS_READY(mmio_read_32(GXBB_AO_RTI_SCP_STAT));
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}
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static inline void gxl_scp_boot(void)
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static inline void gxl_scp_boot(void)
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{
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{
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scpi_upload_scp_fw(bl30_image_info.image_base,
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scpi_upload_scp_fw(bl30_image_info.image_base,
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bl30_image_info.image_size, 0);
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bl30_image_info.image_size, 0);
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scpi_upload_scp_fw(bl301_image_info.image_base,
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scpi_upload_scp_fw(bl301_image_info.image_base,
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bl301_image_info.image_size, 1);
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bl301_image_info.image_size, 1);
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while (!gxl_scp_ready())
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;
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}
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}
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/*******************************************************************************
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/*******************************************************************************
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -91,6 +91,12 @@
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#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
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#define GXBB_SYS_CPU_CFG7 UL(0xC8834664)
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#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
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#define GXBB_AO_RTI_STATUS_REG3 UL(0xDA10001C)
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#define GXBB_AO_RTI_SCP_STAT UL(0xDA10023C)
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#define GXBB_AO_RTI_SCP_READY_OFF U(0x14)
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#define GXBB_A0_RTI_SCP_READY_MASK U(3)
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#define GXBB_AO_RTI_SCP_IS_READY(v) \
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((((v) >> GXBB_AO_RTI_SCP_READY_OFF) & \
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GXBB_A0_RTI_SCP_READY_MASK) == GXBB_A0_RTI_SCP_READY_MASK)
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#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
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#define GXBB_HIU_MAILBOX_SET_0 UL(0xDA83C404)
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#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
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#define GXBB_HIU_MAILBOX_STAT_0 UL(0xDA83C408)
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@ -1,5 +1,5 @@
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/*
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/*
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* Copyright (c) 2018, ARM Limited and Contributors. All rights reserved.
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* Copyright (c) 2018-2019, ARM Limited and Contributors. All rights reserved.
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*
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*
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* SPDX-License-Identifier: BSD-3-Clause
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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*/
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@ -27,20 +27,29 @@
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static uintptr_t gxbb_sec_entrypoint;
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static uintptr_t gxbb_sec_entrypoint;
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static volatile uint32_t gxbb_cpu0_go;
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static volatile uint32_t gxbb_cpu0_go;
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static void gxbb_program_mailbox(u_register_t mpidr, uint64_t value)
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static void gxl_pm_set_reset_addr(u_register_t mpidr, uint64_t value)
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{
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{
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
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uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4);
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mmio_write_64(cpu_mailbox_addr, value);
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mmio_write_64(cpu_mailbox_addr, value);
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flush_dcache_range(cpu_mailbox_addr, sizeof(uint64_t));
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}
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static void gxl_pm_reset(u_register_t mpidr)
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{
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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uintptr_t cpu_mailbox_addr = GXBB_PSCI_MAILBOX_BASE + (core << 4) + 8;
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mmio_write_32(cpu_mailbox_addr, 0);
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}
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}
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static void __dead2 gxbb_system_reset(void)
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static void __dead2 gxbb_system_reset(void)
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{
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{
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INFO("BL31: PSCI_SYSTEM_RESET\n");
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INFO("BL31: PSCI_SYSTEM_RESET\n");
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u_register_t mpidr = read_mpidr_el1();
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uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
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uint32_t status = mmio_read_32(GXBB_AO_RTI_STATUS_REG3);
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int ret;
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NOTICE("BL31: Reboot reason: 0x%x\n", status);
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NOTICE("BL31: Reboot reason: 0x%x\n", status);
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@ -50,13 +59,15 @@ static void __dead2 gxbb_system_reset(void)
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mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
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mmio_write_32(GXBB_AO_RTI_STATUS_REG3, status);
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int ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
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ret = scpi_sys_power_state(SCPI_SYSTEM_REBOOT);
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if (ret != 0) {
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if (ret != 0) {
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ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %u\n", ret);
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ERROR("BL31: PSCI_SYSTEM_RESET: SCP error: %i\n", ret);
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panic();
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panic();
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}
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}
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gxl_pm_reset(mpidr);
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wfi();
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wfi();
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ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
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ERROR("BL31: PSCI_SYSTEM_RESET: Operation not handled\n");
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@ -67,14 +78,18 @@ static void __dead2 gxbb_system_off(void)
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{
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{
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INFO("BL31: PSCI_SYSTEM_OFF\n");
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INFO("BL31: PSCI_SYSTEM_OFF\n");
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unsigned int ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
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u_register_t mpidr = read_mpidr_el1();
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int ret;
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ret = scpi_sys_power_state(SCPI_SYSTEM_SHUTDOWN);
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if (ret != 0) {
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if (ret != 0) {
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ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %u\n", ret);
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ERROR("BL31: PSCI_SYSTEM_OFF: SCP error %i\n", ret);
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panic();
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panic();
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}
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}
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gxbb_program_mailbox(read_mpidr_el1(), 0);
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gxl_pm_set_reset_addr(mpidr, 0);
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gxl_pm_reset(mpidr);
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wfi();
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wfi();
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@ -101,7 +116,7 @@ static int32_t gxbb_pwr_domain_on(u_register_t mpidr)
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return PSCI_E_SUCCESS;
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return PSCI_E_SUCCESS;
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}
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}
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gxbb_program_mailbox(mpidr, gxbb_sec_entrypoint);
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gxl_pm_set_reset_addr(mpidr, gxbb_sec_entrypoint);
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scpi_set_css_power_state(mpidr,
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scpi_set_css_power_state(mpidr,
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SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
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SCPI_POWER_ON, SCPI_POWER_ON, SCPI_POWER_ON);
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dmbsy();
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dmbsy();
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@ -133,10 +148,6 @@ static void gxbb_pwr_domain_off(const psci_power_state_t *target_state)
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{
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{
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u_register_t mpidr = read_mpidr_el1();
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u_register_t mpidr = read_mpidr_el1();
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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unsigned int core = plat_gxbb_calc_core_pos(mpidr);
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uintptr_t addr = GXBB_PSCI_MAILBOX_BASE + 8 + (core << 4);
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mmio_write_32(addr, 0xFFFFFFFF);
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flush_dcache_range(addr, sizeof(uint32_t));
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gicv2_cpuif_disable();
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gicv2_cpuif_disable();
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