SPMD: secondary cores PM on and off SPD hooks relayed to SPMC
Define SPMD PM hooks for warm boot and off events. svc_on_finish handler enters the SPMC at the entry point defined by the secondary EP register service. The svc_off handler notifies the SPMC that a physical core is being turned off through a notification message. Signed-off-by: Olivier Deprez <olivier.deprez@arm.com> Change-Id: I2609a75a0c6ffb9f6313fc09553be2b29a41de59
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@ -59,6 +59,14 @@ entry_point_info_t *spmd_spmc_ep_info_get(void)
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return spmc_ep_info;
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}
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/*******************************************************************************
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* SPM Core ID getter.
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******************************************************************************/
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uint16_t spmd_spmc_id_get(void)
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{
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return spmc_attrs.spmc_id;
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}
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/*******************************************************************************
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* Static function declaration.
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******************************************************************************/
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@ -378,9 +386,9 @@ static bool spmd_is_spmc_message(unsigned int ep)
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/******************************************************************************
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* spmd_handle_spmc_message
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*****************************************************************************/
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static int32_t spmd_handle_spmc_message(uint64_t msg, uint64_t parm1,
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uint64_t parm2, uint64_t parm3,
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uint64_t parm4)
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static int spmd_handle_spmc_message(unsigned long long msg,
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unsigned long long parm1, unsigned long long parm2,
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unsigned long long parm3, unsigned long long parm4)
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{
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VERBOSE("%s %llx %llx %llx %llx %llx\n", __func__,
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msg, parm1, parm2, parm3, parm4);
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@ -6,6 +6,7 @@
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#include <assert.h>
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#include <errno.h>
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#include <lib/el3_runtime/context_mgmt.h>
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#include "spmd_private.h"
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struct spmd_pm_secondary_ep_t {
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@ -16,11 +17,26 @@ struct spmd_pm_secondary_ep_t {
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static struct spmd_pm_secondary_ep_t spmd_pm_secondary_ep[PLATFORM_CORE_COUNT];
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/*******************************************************************************
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* spmd_build_spmc_message
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*
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* Builds an SPMD to SPMC direct message request.
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******************************************************************************/
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static void spmd_build_spmc_message(gp_regs_t *gpregs, unsigned long long message)
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{
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write_ctx_reg(gpregs, CTX_GPREG_X0, FFA_MSG_SEND_DIRECT_REQ_SMC32);
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write_ctx_reg(gpregs, CTX_GPREG_X1,
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(SPMD_DIRECT_MSG_ENDPOINT_ID << FFA_DIRECT_MSG_SOURCE_SHIFT) |
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spmd_spmc_id_get());
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write_ctx_reg(gpregs, CTX_GPREG_X2, FFA_PARAM_MBZ);
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write_ctx_reg(gpregs, CTX_GPREG_X3, message);
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}
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/*******************************************************************************
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* spmd_pm_secondary_core_set_ep
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******************************************************************************/
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int32_t spmd_pm_secondary_core_set_ep(uint64_t mpidr, uintptr_t entry_point,
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uint64_t context)
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int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
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uintptr_t entry_point, unsigned long long context)
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{
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int id = plat_core_pos_by_mpidr(mpidr);
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@ -63,21 +79,77 @@ int32_t spmd_pm_secondary_core_set_ep(uint64_t mpidr, uintptr_t entry_point,
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******************************************************************************/
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static void spmd_cpu_on_finish_handler(u_register_t unused)
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{
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unsigned int linear_id = plat_my_core_pos();
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entry_point_info_t *spmc_ep_info = spmd_spmc_ep_info_get();
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spmd_spm_core_context_t *ctx = spmd_get_context();
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unsigned int linear_id = plat_my_core_pos();
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int rc;
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assert(ctx != NULL);
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assert(ctx->state != SPMC_STATE_ON);
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assert(spmc_ep_info != NULL);
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/*
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* TODO: this might require locking the spmc_ep_info structure,
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* or provisioning one structure per cpu
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*/
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if (spmd_pm_secondary_ep[linear_id].entry_point == 0) {
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goto exit;
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}
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spmc_ep_info->pc = spmd_pm_secondary_ep[linear_id].entry_point;
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cm_setup_context(&ctx->cpu_ctx, spmc_ep_info);
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write_ctx_reg(get_gpregs_ctx(&ctx->cpu_ctx), CTX_GPREG_X0,
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spmd_pm_secondary_ep[linear_id].context);
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/* Mark CPU as initiating ON operation */
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ctx->state = SPMC_STATE_ON_PENDING;
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rc = spmd_spm_core_sync_entry(ctx);
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if (rc != 0) {
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ERROR("SPMC initialisation failed (%d) on CPU%u\n", rc,
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linear_id);
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ERROR("%s failed failed (%d) on CPU%u\n", __func__, rc,
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linear_id);
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ctx->state = SPMC_STATE_OFF;
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return;
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}
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exit:
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ctx->state = SPMC_STATE_ON;
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VERBOSE("CPU %u on!\n", linear_id);
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}
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/*******************************************************************************
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* spmd_cpu_off_handler
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******************************************************************************/
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static int32_t spmd_cpu_off_handler(u_register_t unused)
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{
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spmd_spm_core_context_t *ctx = spmd_get_context();
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unsigned int linear_id = plat_my_core_pos();
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int32_t rc;
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assert(ctx != NULL);
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assert(ctx->state != SPMC_STATE_OFF);
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if (spmd_pm_secondary_ep[linear_id].entry_point == 0) {
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goto exit;
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}
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/* Build an SPMD to SPMC direct message request. */
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spmd_build_spmc_message(get_gpregs_ctx(&ctx->cpu_ctx), PSCI_CPU_OFF);
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rc = spmd_spm_core_sync_entry(ctx);
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if (rc != 0) {
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ERROR("%s failed (%d) on CPU%u\n", __func__, rc, linear_id);
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}
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/* TODO expect FFA_DIRECT_MSG_RESP returned from SPMC */
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exit:
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ctx->state = SPMC_STATE_OFF;
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VERBOSE("CPU %u off!\n", linear_id);
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return 0;
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}
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/*******************************************************************************
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@ -86,4 +158,5 @@ static void spmd_cpu_on_finish_handler(u_register_t unused)
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******************************************************************************/
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const spd_pm_ops_t spmd_pm = {
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.svc_on_finish = spmd_cpu_on_finish_handler,
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.svc_off = spmd_cpu_off_handler
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};
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@ -78,11 +78,14 @@ extern const spd_pm_ops_t spmd_pm;
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/* SPMC entry point information helper */
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entry_point_info_t *spmd_spmc_ep_info_get(void);
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/* SPMC ID getter */
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uint16_t spmd_spmc_id_get(void);
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/* SPMC context on current CPU get helper */
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spmd_spm_core_context_t *spmd_get_context(void);
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int32_t spmd_pm_secondary_core_set_ep(uint64_t mpidr, uintptr_t entry_point,
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uint64_t context);
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int spmd_pm_secondary_core_set_ep(unsigned long long mpidr,
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uintptr_t entry_point, unsigned long long context);
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bool spmd_check_address_in_binary_image(uint64_t address);
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#endif /* __ASSEMBLER__ */
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