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rockchip: update the raw read/write APIs for M0 

Since the ATF project, we usually use the mmio_read_32 and
mmio_write_32. And the mmio_write_32, the firse parameter
is ADDR, the second is VALUE. In order to style consistency:

1/ rename readl/writel to mmio_read_32/mmio_write_32
2/ for keeping the same with mmio_write_32 in the ATF project,
   swap the order of the parameters for M0 mmio_write_32

Signed-off-by: Xing Zheng <zhengxing@rock-chips.com>
Signed-off-by: Lin Huang <hl@rock-chips.com>
This commit is contained in:
Xing Zheng 2016-10-24 21:06:25 +08:00
parent 9a6376c8a1
commit a9a4d23a7d
2 changed files with 8 additions and 8 deletions
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4
plat/rockchip/rk3399/drivers/m0/include/rk3399_mcu.h
View File

@ -31,9 +31,9 @@
#ifndef __RK3399_MCU_H__
#define __RK3399_MCU_H__
#define readl(c) ({unsigned int __v = \
#define mmio_read_32(c) ({unsigned int __v = \
(*(volatile unsigned int *)(c)); __v; })
#define writel(v, c) ((*(volatile unsigned int *) (c)) = (v))
#define mmio_write_32(c, v) ((*(volatile unsigned int *)(c)) = (v))
#define MCU_BASE 0x40000000
#define PMU_BASE (MCU_BASE + 0x07310000)

12
plat/rockchip/rk3399/drivers/m0/src/main.c
View File

@ -43,11 +43,11 @@ static void system_wakeup(void)
unsigned int mode_con;
while (1) {
status_value = readl(PMU_BASE + PMU_POWER_ST);
status_value = mmio_read_32(PMU_BASE + PMU_POWER_ST);
if (status_value) {
mode_con = readl(PMU_BASE + PMU_PWRMODE_CON);
writel(mode_con & (~0x01),
PMU_BASE + PMU_PWRMODE_CON);
mode_con = mmio_read_32(PMU_BASE + PMU_PWRMODE_CON);
mmio_write_32(PMU_BASE + PMU_PWRMODE_CON,
mode_con & (~0x01));
return;
}
}
@ -59,10 +59,10 @@ int main(void)
system_wakeup();
reg_src = readl(M0_SCR);
reg_src = mmio_read_32(M0_SCR);
/* m0 enter deep sleep mode */
writel(reg_src | SCR_SLEEPDEEP_SHIFT, M0_SCR);
mmio_write_32(M0_SCR, reg_src | SCR_SLEEPDEEP_SHIFT);
for (;;)
__asm volatile("wfi");