Tegra: fix defects flagged by MISRA Rule 10.3
MISRA Rule 10.3, the value of an expression shall not be assigned to an object with a narrower essential type or of a different essential type category. The essential type of a enum member is anonymous enum, the enum member should be casted to the right type when using it. Both UL and ULL suffix equal to uint64_t constant in compiler aarch64-linux-gnu-gcc, to avoid confusing, only keep U and ULL suffix in platform code. So in some case, cast a constant to uint32_t is necessary. Change-Id: I1aae8cba81ef47481736e7f95f53570de7013187 Signed-off-by: Anthony Zhou <anzhou@nvidia.com>
This commit is contained in:
Anthony Zhou
Varun Wadekar
parent
e680a39714
commit
aa64c5fb67
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@ -76,7 +76,7 @@ int32_t tegra_bpmp_send_receive_atomic(int mrq, const void *ob_data, int ob_sz,
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/* signal command ready to the BPMP */
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signal_slave(ch);
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mmio_write_32(TEGRA_PRI_ICTLR_BASE + CPU_IEP_FIR_SET,
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(1UL << INT_SHR_SEM_OUTBOX_FULL));
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(1U << INT_SHR_SEM_OUTBOX_FULL));
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/* loop until the command is executed */
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for (timeout = 0; timeout < BPMP_TIMEOUT_10US; timeout++) {
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@ -154,7 +154,7 @@ int tegra_bpmp_init(void)
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channel_base[ch] = mmio_read_32(base);
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/* increment result register offset */
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base += 4UL;
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base += 4U;
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}
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/* mark state as "initialized" */
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@ -302,24 +302,24 @@ static void tegra_memctrl_set_overrides(void)
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*/
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if ((tegra_chipid_is_t186()) &&
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(!tegra_platform_is_silicon() ||
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(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1)))) {
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(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
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/*
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* GPU and NVENC settings for Tegra186 simulation and
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* Silicon rev. A01
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*/
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val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
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val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
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val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
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val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
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val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
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val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
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val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
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val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
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val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
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@ -330,7 +330,7 @@ static void tegra_memctrl_set_overrides(void)
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*/
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for (i = 0; i < num_txn_override_cfgs; i++) {
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val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
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val &= ~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
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tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
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val | mc_txn_override_cfgs[i].cgid_tag);
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}
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@ -421,7 +421,7 @@ void tegra_memctrl_restore_settings(void)
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tegra_memctrl_set_overrides();
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/* video memory carveout region */
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if (video_mem_base) {
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if (video_mem_base != 0ULL) {
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_LO,
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(uint32_t)video_mem_base);
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tegra_mc_write_32(MC_VIDEO_PROTECT_BASE_HI,
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@ -19,7 +19,7 @@ extern void memcpy16(void *dest, const void *src, unsigned int length);
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/* SMMU IDs currently supported by the driver */
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enum {
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TEGRA_SMMU0,
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TEGRA_SMMU0 = 0U,
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TEGRA_SMMU1,
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TEGRA_SMMU2
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};
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@ -86,8 +86,8 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
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/* sanity check SMMU settings c*/
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reg_id1 = mmio_read_32((TEGRA_SMMU0_BASE + SMMU_GNSR0_IDR1));
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pgshift = ((reg_id1 & ID1_PAGESIZE) != 0U) ? 16U : 12U;
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cb_size = (2UL << pgshift) * \
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(1UL << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1UL));
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cb_size = ((uint32_t)2 << pgshift) * \
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((uint32_t)1 << (((reg_id1 >> ID1_NUMPAGENDXB_SHIFT) & ID1_NUMPAGENDXB_MASK) + 1U));
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assert(!((pgshift != PGSHIFT) || (cb_size != CB_SIZE)));
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assert((smmu_ctx_addr >= tzdram_base) && (smmu_ctx_addr <= tzdram_end));
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@ -111,8 +111,9 @@ void tegra_smmu_save_context(uint64_t smmu_ctx_addr)
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}
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/* save SMMU register values */
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for (i = 1; i < num_entries; i++)
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for (i = 1U; i < num_entries; i++) {
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smmu_ctx_regs[i].val = mmio_read_32(smmu_ctx_regs[i].reg);
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}
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/* increment by 1 to take care of the last entry */
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num_entries++;
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@ -139,17 +140,16 @@ void tegra_smmu_init(void)
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uint32_t val, cb_idx, smmu_id, ctx_base;
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uint32_t smmu_counter = plat_get_num_smmu_devices();
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for (smmu_id = 0UL; smmu_id < smmu_counter; smmu_id++) {
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for (smmu_id = 0U; smmu_id < smmu_counter; smmu_id++) {
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/* Program the SMMU pagesize and reset CACHE_LOCK bit */
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val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
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val |= SMMU_GSR0_PGSIZE_64K;
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val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
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/* reset CACHE LOCK bit for NS Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
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val &= ~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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val &= (uint32_t)~SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
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/* disable TCU prefetch for all contexts */
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@ -158,19 +158,19 @@ void tegra_smmu_init(void)
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for (cb_idx = 0; cb_idx < SMMU_CONTEXT_BANK_MAX_IDX; cb_idx++) {
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val = tegra_smmu_read_32(smmu_id,
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ctx_base + (SMMU_GSR0_PGSIZE_64K * cb_idx));
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val &= ~SMMU_CBn_ACTLR_CPRE_BIT;
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val &= (uint32_t)~SMMU_CBn_ACTLR_CPRE_BIT;
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tegra_smmu_write_32(smmu_id, ctx_base +
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(SMMU_GSR0_PGSIZE_64K * cb_idx), val);
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}
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/* set CACHE LOCK bit for NS Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GNSR_ACR);
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val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GNSR_ACR, val);
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/* set CACHE LOCK bit for S Aux. Config. Register */
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val = tegra_smmu_read_32(smmu_id, SMMU_GSR0_SECURE_ACR);
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val |= SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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val |= (uint32_t)SMMU_ACR_CACHE_LOCK_ENABLE_BIT;
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tegra_smmu_write_32(smmu_id, SMMU_GSR0_SECURE_ACR, val);
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}
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}
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@ -98,7 +98,7 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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*/
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if (((x1 & 0xFFFFFU) != 0U) || ((local_x2_32 & 0xFFFFFU) != 0U)) {
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ERROR("Unaligned Video Memory base address!\n");
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SMC_RET1(handle, -ENOTSUP);
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SMC_RET1(handle, (uint64_t)-ENOTSUP);
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}
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/*
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@ -108,9 +108,9 @@ uintptr_t tegra_sip_handler(uint32_t smc_fid,
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*/
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regval = mmio_read_32(TEGRA_CAR_RESET_BASE +
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TEGRA_GPU_RESET_REG_OFFSET);
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if ((regval & GPU_RESET_BIT) == 0UL) {
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if ((regval & GPU_RESET_BIT) == 0U) {
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ERROR("GPU not in reset! Video Memory setup failed\n");
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SMC_RET1(handle, -ENOTSUP);
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SMC_RET1(handle, (uint64_t)-ENOTSUP);
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}
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/* new video memory carveout settings */
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@ -10,25 +10,25 @@
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#include <stdint.h>
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/* macro to enable clock to the Atomics block */
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#define CAR_ENABLE_ATOMICS (1UL << 16)
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#define CAR_ENABLE_ATOMICS (1U << 16)
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/* command to get the channel base addresses from bpmp */
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#define ATOMIC_CMD_GET 4UL
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#define ATOMIC_CMD_GET 4U
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/* Hardware IRQ # used to signal bpmp of an incoming command */
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#define INT_SHR_SEM_OUTBOX_FULL 6UL
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#define INT_SHR_SEM_OUTBOX_FULL 6U
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/* macros to decode the bpmp's state */
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#define CH_MASK(ch) (0x3UL << ((ch) * 2UL))
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#define MA_FREE(ch) (0x2UL << ((ch) * 2UL))
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#define MA_ACKD(ch) (0x3UL << ((ch) * 2UL))
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#define CH_MASK(ch) ((uint32_t)0x3 << ((ch) * 2U))
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#define MA_FREE(ch) ((uint32_t)0x2 << ((ch) * 2U))
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#define MA_ACKD(ch) ((uint32_t)0x3 << ((ch) * 2U))
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/* response from bpmp to indicate it has powered up */
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#define SIGN_OF_LIFE 0xAAAAAAAAUL
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#define SIGN_OF_LIFE 0xAAAAAAAAU
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/* flags to indicate bpmp driver's state */
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#define BPMP_INIT_COMPLETE 0xBEEFF00DUL
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#define BPMP_INIT_PENDING 0xDEADBEEFUL
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#define BPMP_INIT_COMPLETE 0xBEEFF00DU
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#define BPMP_INIT_PENDING 0xDEADBEEFU
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/* requests serviced by the bpmp */
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#define MRQ_PING 0
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@ -64,14 +64,14 @@
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#define TEGRA_PM_SC7 23
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/* flag to indicate if entry into a CCx power state is allowed */
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#define BPMP_CCx_ALLOWED 0UL
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#define BPMP_CCx_ALLOWED 0U
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/* number of communication channels to interact with the bpmp */
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#define NR_CHANNELS 4U
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/* flag to ask bpmp to acknowledge command packet */
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#define NO_ACK (0UL << 0UL)
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#define DO_ACK (1UL << 0UL)
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#define NO_ACK (0U << 0U)
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#define DO_ACK (1U << 0U)
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/* size of the command/response data */
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#define MSG_DATA_MAX_SZ 120U
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@ -17,177 +17,177 @@
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* StreamID to indicate no SMMU translations (requests to be steered on the
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* SMMU bypass path)
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******************************************************************************/
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#define MC_STREAM_ID_MAX 0x7F
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#define MC_STREAM_ID_MAX 0x7FU
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/*******************************************************************************
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* Stream ID Override Config registers
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******************************************************************************/
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#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000
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#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070
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#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8
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#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0
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#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8
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#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158
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#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188
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#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8
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#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8
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#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8
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#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220
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#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230
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#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330
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#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360
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#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368
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#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8
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#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0
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#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0
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#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8
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#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400
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#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408
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#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420
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#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438
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#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440
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#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448
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#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460
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#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468
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#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470
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#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480
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#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490
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#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498
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#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8
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#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0
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#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8
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#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8
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#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0
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#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8
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#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8
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#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8
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#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500
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#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508
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#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510
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#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518
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#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000U
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#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070U
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#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8U
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#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0U
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0U
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#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8U
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#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
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#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
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#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188U
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#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8U
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#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8U
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#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8U
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#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
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#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
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#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
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#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
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#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0U
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#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro to calculate Security cfg register addr from StreamID Override register
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + sizeof(uint32_t))
|
||||
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0UL << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1UL << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2UL << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3UL << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0UL << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1UL << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2UL << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3UL << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0UL << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1UL << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller transaction override config registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure to hold the transaction override settings to use to override
|
||||
|
|
@ -223,12 +223,12 @@ typedef struct mc_streamid_security_cfg {
|
|||
int override_client_ns_flag;
|
||||
} mc_streamid_security_cfg_t;
|
||||
|
||||
#define OVERRIDE_DISABLE 1
|
||||
#define OVERRIDE_ENABLE 0
|
||||
#define CLIENT_FLAG_SECURE 0
|
||||
#define CLIENT_FLAG_NON_SECURE 1
|
||||
#define CLIENT_INPUTS_OVERRIDE 1
|
||||
#define CLIENT_INPUTS_NO_OVERRIDE 0
|
||||
#define OVERRIDE_DISABLE 1U
|
||||
#define OVERRIDE_ENABLE 0U
|
||||
#define CLIENT_FLAG_SECURE 0U
|
||||
#define CLIENT_FLAG_NON_SECURE 1U
|
||||
#define CLIENT_INPUTS_OVERRIDE 1U
|
||||
#define CLIENT_INPUTS_NO_OVERRIDE 0U
|
||||
|
||||
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
|
||||
{ \
|
||||
|
|
@ -257,70 +257,70 @@ typedef struct tegra_mc_settings {
|
|||
/*******************************************************************************
|
||||
* Memory Controller SMMU Bypass config register
|
||||
******************************************************************************/
|
||||
#define MC_SMMU_BYPASS_CONFIG 0x1820
|
||||
#define MC_SMMU_BYPASS_CTRL_MASK 0x3
|
||||
#define MC_SMMU_BYPASS_CTRL_SHIFT 0
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0 << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_RSVD (1 << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2 << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3 << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1 << 31)
|
||||
#define MC_SMMU_BYPASS_CONFIG 0x1820U
|
||||
#define MC_SMMU_BYPASS_CTRL_MASK 0x3U
|
||||
#define MC_SMMU_BYPASS_CTRL_SHIFT 0U
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
|
||||
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
|
||||
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1 << 0)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2 << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1 << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
|
||||
* MC_TXN_OVERRIDE_CONFIG_{module} registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3U
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller Reset Control registers
|
||||
******************************************************************************/
|
||||
#define MC_CLIENT_HOTRESET_CTRL0 0x200
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1 << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1 << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1 << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1 << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1 << 9)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1 << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1 << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1 << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1 << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1 << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1 << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1 << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1 << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1 << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1 << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1 << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1 << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1 << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1 << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1 << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1 << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1 << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1 << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1 << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1 << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1 << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1 << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1 << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1 << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1 << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974
|
||||
#define MC_CLIENT_HOTRESET_CTRL0 0x200U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller's PCFIFO client configuration registers
|
||||
|
|
@ -396,7 +396,7 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
|
|||
}
|
||||
|
||||
#define mc_set_pcfifo_unordered_boot_so_mss(id, client) \
|
||||
(~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
|
||||
((uint32_t)~MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_MASK | \
|
||||
MC_PCFIFO_CLIENT_CONFIG##id##_PCFIFO_##client##_UNORDERED)
|
||||
|
||||
#define mc_set_pcfifo_ordered_boot_so_mss(id, client) \
|
||||
|
|
|
|||
|
|
@ -586,12 +586,12 @@
|
|||
/*******************************************************************************
|
||||
* SMMU Global Aux. Control Register
|
||||
******************************************************************************/
|
||||
#define SMMU_CBn_ACTLR_CPRE_BIT (1UL << 1UL)
|
||||
#define SMMU_CBn_ACTLR_CPRE_BIT (1ULL << 1U)
|
||||
|
||||
/*******************************************************************************
|
||||
* SMMU configuration constants
|
||||
******************************************************************************/
|
||||
#define ID1_PAGESIZE (1U << 31)
|
||||
#define ID1_PAGESIZE (1U << 31U)
|
||||
#define ID1_NUMPAGENDXB_SHIFT 28U
|
||||
#define ID1_NUMPAGENDXB_MASK 7U
|
||||
#define ID1_NUMS2CB_SHIFT 16U
|
||||
|
|
|
|||
|
|
@ -118,7 +118,7 @@
|
|||
/*******************************************************************************
|
||||
* Tegra General Purpose Centralised DMA constants
|
||||
******************************************************************************/
|
||||
#define TEGRA_GPCDMA_BASE U(0x2610000)
|
||||
#define TEGRA_GPCDMA_BASE ULL(0x2610000)
|
||||
|
||||
/*******************************************************************************
|
||||
* Tegra Memory Controller constants
|
||||
|
|
|
|||
|
|
@ -164,7 +164,7 @@
|
|||
#define MC_VIDEO_PROTECT_SIZE_MB U(0x64c)
|
||||
|
||||
/* SMMU configuration registers*/
|
||||
#define MC_SMMU_PPCS_ASID_0 0x270UL
|
||||
#define MC_SMMU_PPCS_ASID_0 0x270U
|
||||
#define PPCS_SMMU_ENABLE (0x1U << 31)
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -151,7 +151,7 @@ int32_t ari_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
|
|||
|
||||
/* Enter the cstate, to be woken up after wake_time (TSC ticks) */
|
||||
ret = ari_request_wait(ari_base, ARI_EVT_MASK_STANDBYWFI_BIT,
|
||||
TEGRA_ARI_ENTER_CSTATE, state, wake_time);
|
||||
(uint32_t)TEGRA_ARI_ENTER_CSTATE, state, wake_time);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -191,7 +191,7 @@ int32_t ari_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccp
|
|||
}
|
||||
|
||||
/* set the updated cstate info */
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CSTATE_INFO,
|
||||
return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_UPDATE_CSTATE_INFO,
|
||||
(uint32_t)val, wake_mask);
|
||||
}
|
||||
|
||||
|
|
@ -208,8 +208,8 @@ int32_t ari_update_crossover_time(uint32_t ari_base, uint32_t type, uint32_t tim
|
|||
ari_clobber_response(ari_base);
|
||||
|
||||
/* update crossover threshold time */
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CROSSOVER,
|
||||
type, time);
|
||||
ret = ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_UPDATE_CROSSOVER, type, time);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -227,7 +227,8 @@ uint64_t ari_read_cstate_stats(uint32_t ari_base, uint32_t state)
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_CSTATE_STATS, state, 0U);
|
||||
ret = ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_CSTATE_STATS, state, 0U);
|
||||
if (ret != 0) {
|
||||
result = EINVAL;
|
||||
} else {
|
||||
|
|
@ -243,8 +244,8 @@ int32_t ari_write_cstate_stats(uint32_t ari_base, uint32_t state, uint32_t stats
|
|||
ari_clobber_response(ari_base);
|
||||
|
||||
/* write the cstate stats */
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_WRITE_CSTATE_STATS, state,
|
||||
stats);
|
||||
return ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_WRITE_CSTATE_STATS,
|
||||
state, stats);
|
||||
}
|
||||
|
||||
uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
|
||||
|
|
@ -261,7 +262,7 @@ uint64_t ari_enumeration_misc(uint32_t ari_base, uint32_t cmd, uint32_t data)
|
|||
local_data = 0U;
|
||||
}
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC, cmd, local_data);
|
||||
ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MISC, cmd, local_data);
|
||||
if (ret != 0) {
|
||||
resp = (uint64_t)ret;
|
||||
} else {
|
||||
|
|
@ -281,8 +282,8 @@ int32_t ari_is_ccx_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_CCX_ALLOWED, state & 0x7U,
|
||||
wake_time);
|
||||
ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_IS_CCX_ALLOWED,
|
||||
state & 0x7U, wake_time);
|
||||
if (ret != 0) {
|
||||
ERROR("%s: failed (%d)\n", __func__, ret);
|
||||
result = 0U;
|
||||
|
|
@ -307,8 +308,8 @@ int32_t ari_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_IS_SC7_ALLOWED, state,
|
||||
wake_time);
|
||||
ret = ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_IS_SC7_ALLOWED, state, wake_time);
|
||||
if (ret != 0) {
|
||||
ERROR("%s: failed (%d)\n", __func__, ret);
|
||||
result = 0;
|
||||
|
|
@ -346,7 +347,8 @@ int32_t ari_online_core(uint32_t ari_base, uint32_t core)
|
|||
} else {
|
||||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_ONLINE_CORE, core, 0U);
|
||||
ret = ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_ONLINE_CORE, core, 0U);
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -374,7 +376,8 @@ int32_t ari_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
|
|||
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
|
||||
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
|
||||
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_CC3_CTRL, val, 0U);
|
||||
return ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_CC3_CTRL, val, 0U);
|
||||
}
|
||||
|
||||
int32_t ari_reset_vector_update(uint32_t ari_base)
|
||||
|
|
@ -386,7 +389,8 @@ int32_t ari_reset_vector_update(uint32_t ari_base)
|
|||
* Need to program the CPU reset vector one time during cold boot
|
||||
* and SC7 exit
|
||||
*/
|
||||
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
|
||||
(void)ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_COPY_MISCREG_AA64_RST, 0U, 0U);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -396,8 +400,8 @@ int32_t ari_roc_flush_cache_trbits(uint32_t ari_base)
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS,
|
||||
0U, 0U);
|
||||
return ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_TRBITS, 0U, 0U);
|
||||
}
|
||||
|
||||
int32_t ari_roc_flush_cache(uint32_t ari_base)
|
||||
|
|
@ -405,8 +409,8 @@ int32_t ari_roc_flush_cache(uint32_t ari_base)
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_FLUSH_CACHE_ONLY,
|
||||
0U, 0U);
|
||||
return ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_ROC_FLUSH_CACHE_ONLY, 0U, 0U);
|
||||
}
|
||||
|
||||
int32_t ari_roc_clean_cache(uint32_t ari_base)
|
||||
|
|
@ -414,8 +418,8 @@ int32_t ari_roc_clean_cache(uint32_t ari_base)
|
|||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
|
||||
return ari_request_wait(ari_base, 0U, TEGRA_ARI_ROC_CLEAN_CACHE_ONLY,
|
||||
0U, 0U);
|
||||
return ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_ROC_CLEAN_CACHE_ONLY, 0U, 0U);
|
||||
}
|
||||
|
||||
uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
|
||||
|
|
@ -432,7 +436,7 @@ uint64_t ari_read_write_mca(uint32_t ari_base, uint64_t cmd, uint64_t *data)
|
|||
ari_write_32(ari_base, (uint32_t)cmd, ARI_RESPONSE_DATA_LO);
|
||||
ari_write_32(ari_base, (uint32_t)(cmd >> 32U), ARI_RESPONSE_DATA_HI);
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_MCA,
|
||||
ret = ari_request_wait(ari_base, 0U, (uint32_t)TEGRA_ARI_MCA,
|
||||
(uint32_t)mca_arg_data,
|
||||
(uint32_t)(mca_arg_data >> 32U));
|
||||
if (ret == 0) {
|
||||
|
|
@ -473,7 +477,8 @@ int32_t ari_update_ccplex_gsc(uint32_t ari_base, uint32_t gsc_idx)
|
|||
* the ID, from the MC registers and update the internal GSC registers
|
||||
* of the CCPLEX.
|
||||
*/
|
||||
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
|
||||
(void)ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_UPDATE_CCPLEX_GSC, gsc_idx, 0U);
|
||||
}
|
||||
|
||||
return ret;
|
||||
|
|
@ -487,7 +492,8 @@ void ari_enter_ccplex_state(uint32_t ari_base, uint32_t state_idx)
|
|||
/*
|
||||
* The MCE will shutdown or restart the entire system
|
||||
*/
|
||||
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
|
||||
(void)ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_MISC_CCPLEX, state_idx, 0U);
|
||||
}
|
||||
|
||||
int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
|
||||
|
|
@ -514,8 +520,8 @@ int32_t ari_read_write_uncore_perfmon(uint32_t ari_base, uint64_t req,
|
|||
val = (req_cmd == UNCORE_PERFMON_CMD_WRITE) ?
|
||||
(uint32_t)*data : 0U;
|
||||
|
||||
ret = ari_request_wait(ari_base, 0U, TEGRA_ARI_PERFMON, val,
|
||||
(uint32_t)req);
|
||||
ret = ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_PERFMON, val, (uint32_t)req);
|
||||
if (ret != 0) {
|
||||
result = ret;
|
||||
} else {
|
||||
|
|
@ -552,6 +558,7 @@ void ari_misc_ccplex(uint32_t ari_base, uint32_t index, uint32_t value)
|
|||
} else {
|
||||
/* clean the previous response state */
|
||||
ari_clobber_response(ari_base);
|
||||
(void)ari_request_wait(ari_base, 0U, TEGRA_ARI_MISC_CCPLEX, index, value);
|
||||
(void)ari_request_wait(ari_base, 0U,
|
||||
(uint32_t)TEGRA_ARI_MISC_CCPLEX, index, value);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -170,12 +170,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
cpu_ari_base = mce_get_curr_cpu_ari_base();
|
||||
|
||||
switch (cmd) {
|
||||
case MCE_CMD_ENTER_CSTATE:
|
||||
case (uint64_t)MCE_CMD_ENTER_CSTATE:
|
||||
ret = ops->enter_cstate(cpu_ari_base, arg0, arg1);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_UPDATE_CSTATE_INFO:
|
||||
case (uint64_t)MCE_CMD_UPDATE_CSTATE_INFO:
|
||||
/*
|
||||
* get the parameters required for the update cstate info
|
||||
* command
|
||||
|
|
@ -194,12 +194,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_UPDATE_CROSSOVER_TIME:
|
||||
case (uint64_t)MCE_CMD_UPDATE_CROSSOVER_TIME:
|
||||
ret = ops->update_crossover_time(cpu_ari_base, arg0, arg1);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_READ_CSTATE_STATS:
|
||||
case (uint64_t)MCE_CMD_READ_CSTATE_STATS:
|
||||
ret64 = ops->read_cstate_stats(cpu_ari_base, arg0);
|
||||
|
||||
/* update context to return cstate stats value */
|
||||
|
|
@ -208,12 +208,12 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_WRITE_CSTATE_STATS:
|
||||
case (uint64_t)MCE_CMD_WRITE_CSTATE_STATS:
|
||||
ret = ops->write_cstate_stats(cpu_ari_base, arg0, arg1);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_IS_CCX_ALLOWED:
|
||||
case (uint64_t)MCE_CMD_IS_CCX_ALLOWED:
|
||||
ret = ops->is_ccx_allowed(cpu_ari_base, arg0, arg1);
|
||||
|
||||
/* update context to return CCx status value */
|
||||
|
|
@ -221,7 +221,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_IS_SC7_ALLOWED:
|
||||
case (uint64_t)MCE_CMD_IS_SC7_ALLOWED:
|
||||
ret = ops->is_sc7_allowed(cpu_ari_base, arg0, arg1);
|
||||
|
||||
/* update context to return SC7 status value */
|
||||
|
|
@ -230,17 +230,17 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ONLINE_CORE:
|
||||
case (uint64_t)MCE_CMD_ONLINE_CORE:
|
||||
ret = ops->online_core(cpu_ari_base, arg0);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_CC3_CTRL:
|
||||
case (uint64_t)MCE_CMD_CC3_CTRL:
|
||||
ret = ops->cc3_ctrl(cpu_ari_base, arg0, arg1, arg2);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ECHO_DATA:
|
||||
case (uint64_t)MCE_CMD_ECHO_DATA:
|
||||
ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_ECHO,
|
||||
arg0);
|
||||
|
||||
|
|
@ -252,7 +252,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_READ_VERSIONS:
|
||||
case (uint64_t)MCE_CMD_READ_VERSIONS:
|
||||
ret64 = ops->call_enum_misc(cpu_ari_base, TEGRA_ARI_MISC_VERSION,
|
||||
arg0);
|
||||
|
||||
|
|
@ -265,7 +265,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ENUM_FEATURES:
|
||||
case (uint64_t)MCE_CMD_ENUM_FEATURES:
|
||||
ret64 = ops->call_enum_misc(cpu_ari_base,
|
||||
TEGRA_ARI_MISC_FEATURE_LEAF_0, arg0);
|
||||
|
||||
|
|
@ -274,22 +274,22 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
|
||||
case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE_TRBITS:
|
||||
ret = ops->roc_flush_cache_trbits(cpu_ari_base);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ROC_FLUSH_CACHE:
|
||||
case (uint64_t)MCE_CMD_ROC_FLUSH_CACHE:
|
||||
ret = ops->roc_flush_cache(cpu_ari_base);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ROC_CLEAN_CACHE:
|
||||
case (uint64_t)MCE_CMD_ROC_CLEAN_CACHE:
|
||||
ret = ops->roc_clean_cache(cpu_ari_base);
|
||||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ENUM_READ_MCA:
|
||||
case (uint64_t)MCE_CMD_ENUM_READ_MCA:
|
||||
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
|
||||
|
||||
/* update context to return MCA data/error */
|
||||
|
|
@ -299,7 +299,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
|
||||
break;
|
||||
|
||||
case MCE_CMD_ENUM_WRITE_MCA:
|
||||
case (uint64_t)MCE_CMD_ENUM_WRITE_MCA:
|
||||
ret64 = ops->read_write_mca(cpu_ari_base, arg0, &arg1);
|
||||
|
||||
/* update context to return MCA error */
|
||||
|
|
@ -309,7 +309,7 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
break;
|
||||
|
||||
#if ENABLE_CHIP_VERIFICATION_HARNESS
|
||||
case MCE_CMD_ENABLE_LATIC:
|
||||
case (uint64_t)MCE_CMD_ENABLE_LATIC:
|
||||
/*
|
||||
* This call is not for production use. The constant value,
|
||||
* 0xFFFF0000, is specific to allowing for enabling LATIC on
|
||||
|
|
@ -327,14 +327,14 @@ int32_t mce_command_handler(uint64_t cmd, uint64_t arg0, uint64_t arg1,
|
|||
break;
|
||||
#endif
|
||||
|
||||
case MCE_CMD_UNCORE_PERFMON_REQ:
|
||||
case (uint64_t)MCE_CMD_UNCORE_PERFMON_REQ:
|
||||
ret = ops->read_write_uncore_perfmon(cpu_ari_base, arg0, &arg1);
|
||||
|
||||
/* update context to return data */
|
||||
write_ctx_reg(gp_regs, CTX_GPREG_X1, (arg1));
|
||||
break;
|
||||
|
||||
case MCE_CMD_MISC_CCPLEX:
|
||||
case (uint64_t)MCE_CMD_MISC_CCPLEX:
|
||||
ops->misc_ccplex(cpu_ari_base, arg0, arg1);
|
||||
|
||||
break;
|
||||
|
|
|
|||
|
|
@ -30,7 +30,7 @@ int32_t nvg_enter_cstate(uint32_t ari_base, uint32_t state, uint32_t wake_time)
|
|||
ret = EINVAL;
|
||||
} else {
|
||||
/* time (TSC ticks) until the core is expected to get a wake event */
|
||||
nvg_set_request_data(TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
|
||||
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_WAKE_TIME, wake_time);
|
||||
|
||||
/* set the core cstate */
|
||||
val = read_actlr_el1() & ~ACTLR_EL1_PMSTATE_MASK;
|
||||
|
|
@ -81,7 +81,7 @@ int32_t nvg_update_cstate_info(uint32_t ari_base, uint32_t cluster, uint32_t ccp
|
|||
val |= ((uint64_t)wake_mask << CSTATE_WAKE_MASK_SHIFT);
|
||||
|
||||
/* set the updated cstate info */
|
||||
nvg_set_request_data(TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
|
||||
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CSTATE_INFO, val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
@ -192,7 +192,7 @@ int32_t nvg_is_sc7_allowed(uint32_t ari_base, uint32_t state, uint32_t wake_time
|
|||
((uint64_t)state & MCE_SC7_ALLOWED_MASK);
|
||||
|
||||
/* issue command to check if SC7 is allowed */
|
||||
nvg_set_request_data(TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
|
||||
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_IS_SC7_ALLOWED, val);
|
||||
|
||||
/* 1 = SC7 allowed, 0 = SC7 not allowed */
|
||||
ret = (nvg_get_result() != 0ULL) ? 1 : 0;
|
||||
|
|
@ -222,7 +222,7 @@ int32_t nvg_online_core(uint32_t ari_base, uint32_t core)
|
|||
ret = EINVAL;
|
||||
} else {
|
||||
/* get a core online */
|
||||
nvg_set_request_data(TEGRA_NVG_CHANNEL_ONLINE_CORE,
|
||||
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_ONLINE_CORE,
|
||||
((uint64_t)core & MCE_CORE_ID_MASK));
|
||||
}
|
||||
}
|
||||
|
|
@ -250,7 +250,7 @@ int32_t nvg_cc3_ctrl(uint32_t ari_base, uint32_t freq, uint32_t volt, uint8_t en
|
|||
((volt & MCE_AUTO_CC3_VTG_MASK) << MCE_AUTO_CC3_VTG_SHIFT) |\
|
||||
((enable != 0U) ? MCE_AUTO_CC3_ENABLE_BIT : 0U));
|
||||
|
||||
nvg_set_request_data(TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);
|
||||
nvg_set_request_data((uint64_t)TEGRA_NVG_CHANNEL_CC3_CTRL, (uint64_t)val);
|
||||
|
||||
return 0;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -206,11 +206,11 @@ const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
|
|||
******************************************************************************/
|
||||
static tegra_mc_settings_t tegra186_mc_settings = {
|
||||
.streamid_override_cfg = tegra186_streamid_override_regs,
|
||||
.num_streamid_override_cfgs = ARRAY_SIZE(tegra186_streamid_override_regs),
|
||||
.num_streamid_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_override_regs),
|
||||
.streamid_security_cfg = tegra186_streamid_sec_cfgs,
|
||||
.num_streamid_security_cfgs = ARRAY_SIZE(tegra186_streamid_sec_cfgs),
|
||||
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
|
||||
.txn_override_cfg = tegra186_txn_override_cfgs,
|
||||
.num_txn_override_cfgs = ARRAY_SIZE(tegra186_txn_override_cfgs)
|
||||
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs)
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -109,7 +109,7 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
|||
|
||||
/* Enter CPU idle/powerdown */
|
||||
val = (stateid_afflvl0 == PSTATE_ID_CORE_IDLE) ?
|
||||
TEGRA_ARI_CORE_C6 : TEGRA_ARI_CORE_C7;
|
||||
(uint32_t)TEGRA_ARI_CORE_C6 : (uint32_t)TEGRA_ARI_CORE_C7;
|
||||
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, (uint64_t)val,
|
||||
tegra_percpu_data[cpu].wake_time, 0U);
|
||||
|
||||
|
|
@ -134,8 +134,8 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
|||
tegra_smmu_save_context((uintptr_t)smmu_ctx_base);
|
||||
|
||||
/* Prepare for system suspend */
|
||||
cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
|
||||
cstate_info.system = TEGRA_ARI_SYSTEM_SC7;
|
||||
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
|
||||
cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC7;
|
||||
cstate_info.system_state_force = 1;
|
||||
cstate_info.update_wake_mask = 1;
|
||||
mce_update_cstate_info(&cstate_info);
|
||||
|
|
@ -143,14 +143,14 @@ int32_t tegra_soc_pwr_domain_suspend(const psci_power_state_t *target_state)
|
|||
do {
|
||||
val = (uint32_t)mce_command_handler(
|
||||
(uint64_t)MCE_CMD_IS_SC7_ALLOWED,
|
||||
TEGRA_ARI_CORE_C7,
|
||||
(uint64_t)TEGRA_ARI_CORE_C7,
|
||||
MCE_CORE_SLEEP_TIME_INFINITE,
|
||||
0U);
|
||||
} while (val == 0U);
|
||||
|
||||
/* Instruct the MCE to enter system suspend state */
|
||||
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
|
||||
TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
||||
(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
||||
} else {
|
||||
; /* do nothing */
|
||||
}
|
||||
|
|
@ -243,12 +243,12 @@ static plat_local_state_t tegra_get_afflvl1_pwr_state(const plat_local_state_t *
|
|||
* Platform handler to calculate the proper target power level at the
|
||||
* specified affinity level
|
||||
******************************************************************************/
|
||||
plat_local_state_t tegra_soc_get_target_pwr_state(unsigned int lvl,
|
||||
plat_local_state_t tegra_soc_get_target_pwr_state(uint32_t lvl,
|
||||
const plat_local_state_t *states,
|
||||
uint32_t ncpu)
|
||||
{
|
||||
plat_local_state_t target = PSCI_LOCAL_STATE_RUN;
|
||||
int cpu = plat_my_core_pos();
|
||||
uint32_t cpu = plat_my_core_pos();
|
||||
|
||||
/* System Suspend */
|
||||
if ((lvl == (uint32_t)MPIDR_AFFLVL2) &&
|
||||
|
|
@ -342,7 +342,7 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
*/
|
||||
if (stateid_afflvl0 == PLAT_MAX_OFF_STATE) {
|
||||
|
||||
cstate_info.cluster = TEGRA_ARI_CLUSTER_CC1;
|
||||
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC1;
|
||||
cstate_info.update_wake_mask = 1;
|
||||
mce_update_cstate_info(&cstate_info);
|
||||
}
|
||||
|
|
@ -369,8 +369,8 @@ int32_t tegra_soc_pwr_domain_on_finish(const psci_power_state_t *target_state)
|
|||
* and SC7 for SC7 entry which may not be requested by
|
||||
* non-secure SW which controls idle states.
|
||||
*/
|
||||
cstate_info.cluster = TEGRA_ARI_CLUSTER_CC7;
|
||||
cstate_info.system = TEGRA_ARI_SYSTEM_SC1;
|
||||
cstate_info.cluster = (uint32_t)TEGRA_ARI_CLUSTER_CC7;
|
||||
cstate_info.system = (uint32_t)TEGRA_ARI_SYSTEM_SC1;
|
||||
cstate_info.update_wake_mask = 1;
|
||||
mce_update_cstate_info(&cstate_info);
|
||||
}
|
||||
|
|
@ -390,8 +390,8 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
|||
}
|
||||
|
||||
/* Turn off CPU */
|
||||
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE, TEGRA_ARI_CORE_C7,
|
||||
MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
||||
(void)mce_command_handler((uint64_t)MCE_CMD_ENTER_CSTATE,
|
||||
(uint64_t)TEGRA_ARI_CORE_C7, MCE_CORE_SLEEP_TIME_INFINITE, 0U);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
@ -399,7 +399,7 @@ int32_t tegra_soc_pwr_domain_off(const psci_power_state_t *target_state)
|
|||
__dead2 void tegra_soc_prepare_system_off(void)
|
||||
{
|
||||
/* power off the entire system */
|
||||
mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
|
||||
mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_POWER_OFF);
|
||||
|
||||
wfi();
|
||||
|
||||
|
|
@ -411,7 +411,7 @@ __dead2 void tegra_soc_prepare_system_off(void)
|
|||
|
||||
int32_t tegra_soc_prepare_system_reset(void)
|
||||
{
|
||||
mce_enter_ccplex_state(TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);
|
||||
mce_enter_ccplex_state((uint32_t)TEGRA_ARI_MISC_CCPLEX_SHUTDOWN_REBOOT);
|
||||
|
||||
return PSCI_E_SUCCESS;
|
||||
}
|
||||
|
|
|
|||
|
|
@ -85,23 +85,23 @@
|
|||
|
||||
#define DRBG_MODE_SHIFT 0
|
||||
#define DRBG_MODE_NORMAL \
|
||||
((0UL) << DRBG_MODE_SHIFT)
|
||||
((0U) << DRBG_MODE_SHIFT)
|
||||
#define DRBG_MODE_FORCE_INSTANTION \
|
||||
((1UL) << DRBG_MODE_SHIFT)
|
||||
((1U) << DRBG_MODE_SHIFT)
|
||||
#define DRBG_MODE_FORCE_RESEED \
|
||||
((2UL) << DRBG_MODE_SHIFT)
|
||||
((2U) << DRBG_MODE_SHIFT)
|
||||
#define SE_RNG_CONFIG_MODE(x) \
|
||||
((x) & ((0x3UL) << DRBG_MODE_SHIFT))
|
||||
((x) & ((0x3U) << DRBG_MODE_SHIFT))
|
||||
|
||||
#define DRBG_SRC_SHIFT 2
|
||||
#define DRBG_SRC_NONE \
|
||||
((0UL) << DRBG_SRC_SHIFT)
|
||||
((0U) << DRBG_SRC_SHIFT)
|
||||
#define DRBG_SRC_ENTROPY \
|
||||
((1UL) << DRBG_SRC_SHIFT)
|
||||
((1U) << DRBG_SRC_SHIFT)
|
||||
#define DRBG_SRC_LFSR \
|
||||
((2UL) << DRBG_SRC_SHIFT)
|
||||
((2U) << DRBG_SRC_SHIFT)
|
||||
#define SE_RNG_SRC_CONFIG_MODE(x) \
|
||||
((x) & ((0x3UL) << DRBG_SRC_SHIFT))
|
||||
((x) & ((0x3U) << DRBG_SRC_SHIFT))
|
||||
|
||||
/* DRBG random number generator entropy config */
|
||||
#define SE_RNG_SRC_CONFIG_REG_OFFSET 0x344U
|
||||
|
|
|
|||
|
|
@ -20,7 +20,7 @@
|
|||
* Constants and Macros
|
||||
******************************************************************************/
|
||||
|
||||
#define TIMEOUT_100MS 100UL // Timeout in 100ms
|
||||
#define TIMEOUT_100MS 100U // Timeout in 100ms
|
||||
|
||||
/*******************************************************************************
|
||||
* Data structure and global variables
|
||||
|
|
|
|||
Loading…
Reference in New Issue