diff --git a/plat/intel/soc/agilex/include/agilex_noc.h b/plat/intel/soc/agilex/include/agilex_noc.h deleted file mode 100644 index 9aba3c33b..000000000 --- a/plat/intel/soc/agilex/include/agilex_noc.h +++ /dev/null @@ -1,69 +0,0 @@ -/* - * Copyright (c) 2019-2022, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#ifndef AGX_NOC_H -#define AGX_NOC_H - - -#define AXI_AP (1<<0) -#define FPGA2SOC (1<<16) -#define MPU (1<<24) -#define AGX_NOC_PER_SCR_NAND 0xffd21000 -#define AGX_NOC_PER_SCR_NAND_DATA 0xffd21004 -#define AGX_NOC_PER_SCR_USB0 0xffd2100c -#define AGX_NOC_PER_SCR_USB1 0xffd21010 -#define AGX_NOC_PER_SCR_SPI_M0 0xffd2101c -#define AGX_NOC_PER_SCR_SPI_M1 0xffd21020 -#define AGX_NOC_PER_SCR_SPI_S0 0xffd21024 -#define AGX_NOC_PER_SCR_SPI_S1 0xffd21028 -#define AGX_NOC_PER_SCR_EMAC0 0xffd2102c -#define AGX_NOC_PER_SCR_EMAC1 0xffd21030 -#define AGX_NOC_PER_SCR_EMAC2 0xffd21034 -#define AGX_NOC_PER_SCR_SDMMC 0xffd21040 -#define AGX_NOC_PER_SCR_GPIO0 0xffd21044 -#define AGX_NOC_PER_SCR_GPIO1 0xffd21048 -#define AGX_NOC_PER_SCR_I2C0 0xffd21050 -#define AGX_NOC_PER_SCR_I2C1 0xffd21058 -#define AGX_NOC_PER_SCR_I2C2 0xffd2105c -#define AGX_NOC_PER_SCR_I2C3 0xffd21060 -#define AGX_NOC_PER_SCR_SP_TIMER0 0xffd21064 -#define AGX_NOC_PER_SCR_SP_TIMER1 0xffd21068 -#define AGX_NOC_PER_SCR_UART0 0xffd2106c -#define AGX_NOC_PER_SCR_UART1 0xffd21070 - - -#define AGX_NOC_SYS_SCR_DMA_ECC 0xffd21108 -#define AGX_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define AGX_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define AGX_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define AGX_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define AGX_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define AGX_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define AGX_NOC_SYS_SCR_NAND_ECC 0xffd2112c -#define AGX_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define AGX_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define AGX_NOC_SYS_SCR_OCRAM_ECC 0xffd21138 -#define AGX_NOC_SYS_SCR_SDMMC_ECC 0xffd21140 -#define AGX_NOC_SYS_SCR_USB0_ECC 0xffd21144 -#define AGX_NOC_SYS_SCR_USB1_ECC 0xffd21148 -#define AGX_NOC_SYS_SCR_CLK_MGR 0xffd2114c -#define AGX_NOC_SYS_SCR_IO_MGR 0xffd21154 -#define AGX_NOC_SYS_SCR_RST_MGR 0xffd21158 -#define AGX_NOC_SYS_SCR_SYS_MGR 0xffd2115c -#define AGX_NOC_SYS_SCR_OSC0_TIMER 0xffd21160 -#define AGX_NOC_SYS_SCR_OSC1_TIMER 0xffd21164 -#define AGX_NOC_SYS_SCR_WATCHDOG0 0xffd21168 -#define AGX_NOC_SYS_SCR_WATCHDOG1 0xffd2116c -#define AGX_NOC_SYS_SCR_WATCHDOG2 0xffd21170 -#define AGX_NOC_SYS_SCR_WATCHDOG3 0xffd21174 -#define AGX_NOC_SYS_SCR_DAP 0xffd21178 -#define AGX_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define AGX_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define AGX_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688 -#define AGX_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688 - -#endif diff --git a/plat/intel/soc/common/include/socfpga_sip_svc.h b/plat/intel/soc/common/include/socfpga_sip_svc.h index f9a6ffdec..0803eb5db 100644 --- a/plat/intel/soc/common/include/socfpga_sip_svc.h +++ b/plat/intel/soc/common/include/socfpga_sip_svc.h @@ -180,6 +180,12 @@ struct fpga_config_info { int block_number; }; +typedef enum { + NO_REQUEST = 0, + RECONFIGURATION, + BITSTREAM_AUTH +} config_type; + /* Function Definitions */ bool is_size_4_bytes_aligned(uint32_t size); bool is_address_in_ddr_range(uint64_t addr, uint64_t size); diff --git a/plat/intel/soc/common/sip/socfpga_sip_fcs.c b/plat/intel/soc/common/sip/socfpga_sip_fcs.c index c4e30a240..eacc4dda1 100644 --- a/plat/intel/soc/common/sip/socfpga_sip_fcs.c +++ b/plat/intel/soc/common/sip/socfpga_sip_fcs.c @@ -315,36 +315,6 @@ uint32_t intel_fcs_decryption(uint32_t src_addr, uint32_t src_size, return INTEL_SIP_SMC_STATUS_OK; } -uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, - uint32_t *mbox_error) -{ - int status; - unsigned int resp_len = FCS_SHA384_WORD_SIZE; - - if (!is_address_in_ddr_range(addr, FCS_SHA384_BYTE_SIZE)) { - return INTEL_SIP_SMC_STATUS_REJECTED; - } - - status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ROM_PATCH_SHA384, NULL, 0U, - CMD_CASUAL, (uint32_t *) addr, &resp_len); - - if (status < 0) { - *mbox_error = -status; - return INTEL_SIP_SMC_STATUS_ERROR; - } - - if (resp_len != FCS_SHA384_WORD_SIZE) { - *mbox_error = GENERIC_RESPONSE_ERROR; - return INTEL_SIP_SMC_STATUS_ERROR; - } - - *ret_size = FCS_SHA384_BYTE_SIZE; - - flush_dcache_range(addr, *ret_size); - - return INTEL_SIP_SMC_STATUS_OK; -} - int intel_fcs_encryption_ext(uint32_t session_id, uint32_t context_id, uint32_t src_addr, uint32_t src_size, uint32_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error) @@ -561,6 +531,36 @@ int intel_fcs_get_measurement(uint64_t src_addr, uint32_t src_size, return INTEL_SIP_SMC_STATUS_OK; } +uint32_t intel_fcs_get_rom_patch_sha384(uint64_t addr, uint64_t *ret_size, + uint32_t *mbox_error) +{ + int status; + unsigned int resp_len = FCS_SHA384_WORD_SIZE; + + if (!is_address_in_ddr_range(addr, FCS_SHA384_BYTE_SIZE)) { + return INTEL_SIP_SMC_STATUS_REJECTED; + } + + status = mailbox_send_cmd(MBOX_JOB_ID, MBOX_GET_ROM_PATCH_SHA384, NULL, 0U, + CMD_CASUAL, (uint32_t *) addr, &resp_len); + + if (status < 0) { + *mbox_error = -status; + return INTEL_SIP_SMC_STATUS_ERROR; + } + + if (resp_len != FCS_SHA384_WORD_SIZE) { + *mbox_error = GENERIC_RESPONSE_ERROR; + return INTEL_SIP_SMC_STATUS_ERROR; + } + + *ret_size = FCS_SHA384_BYTE_SIZE; + + flush_dcache_range(addr, *ret_size); + + return INTEL_SIP_SMC_STATUS_OK; +} + int intel_fcs_get_attestation_cert(uint32_t cert_request, uint64_t dst_addr, uint32_t *dst_size, uint32_t *mbox_error) { diff --git a/plat/intel/soc/common/socfpga_delay_timer.c b/plat/intel/soc/common/socfpga_delay_timer.c index 957738cdd..dcd51e270 100644 --- a/plat/intel/soc/common/socfpga_delay_timer.c +++ b/plat/intel/soc/common/socfpga_delay_timer.c @@ -36,7 +36,6 @@ void socfpga_delay_timer_init_args(void) timer_init(&plat_timer_ops); - NOTICE("BL31: MPU clock frequency: %d MHz\n", plat_timer_ops.clk_div); } void socfpga_delay_timer_init(void) diff --git a/plat/intel/soc/common/socfpga_sip_svc.c b/plat/intel/soc/common/socfpga_sip_svc.c index f7dd3929a..f079349f3 100644 --- a/plat/intel/soc/common/socfpga_sip_svc.c +++ b/plat/intel/soc/common/socfpga_sip_svc.c @@ -19,6 +19,7 @@ /* Total buffer the driver can hold */ #define FPGA_CONFIG_BUFFER_SIZE 4 +static config_type request_type = NO_REQUEST; static int current_block, current_buffer; static int read_block, max_blocks; static uint32_t send_id, rcv_id; @@ -27,10 +28,8 @@ static bool bridge_disable; /* RSU static variables */ static uint32_t rsu_dcmf_ver[4] = {0}; - -/* RSU Max Retry */ -static uint32_t rsu_max_retry; static uint16_t rsu_dcmf_stat[4] = {0}; +static uint32_t rsu_max_retry; /* SiP Service UUID */ DEFINE_SVC_UUID2(intl_svc_uid, @@ -89,28 +88,39 @@ static int intel_fpga_sdm_write_all(void) return 0; } -static uint32_t intel_mailbox_fpga_config_isdone(uint32_t query_type) +static uint32_t intel_mailbox_fpga_config_isdone(void) { uint32_t ret; - if (query_type == 1U) { - ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, false); - } else { - ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, true); + switch (request_type) { + case RECONFIGURATION: + ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, + true); + break; + case BITSTREAM_AUTH: + ret = intel_mailbox_get_config_status(MBOX_RECONFIG_STATUS, + false); + break; + default: + ret = intel_mailbox_get_config_status(MBOX_CONFIG_STATUS, + false); + break; } if (ret != 0U) { if (ret == MBOX_CFGSTAT_STATE_CONFIG) { return INTEL_SIP_SMC_STATUS_BUSY; } else { + request_type = NO_REQUEST; return INTEL_SIP_SMC_STATUS_ERROR; } } - if (bridge_disable) { + if (bridge_disable != 0U) { socfpga_bridges_enable(~0); /* Enable bridge */ bridge_disable = false; } + request_type = NO_REQUEST; return INTEL_SIP_SMC_STATUS_OK; } @@ -169,6 +179,7 @@ static int intel_fpga_config_completed_write(uint32_t *completed_addr, if (status != MBOX_NO_RESPONSE && status != MBOX_TIMEOUT && resp_len != 0) { mailbox_clear_response(); + request_type = NO_REQUEST; return INTEL_SIP_SMC_STATUS_ERROR; } @@ -205,6 +216,8 @@ static int intel_fpga_config_start(uint32_t flag) unsigned int size = 0; unsigned int resp_len = ARRAY_SIZE(response); + request_type = RECONFIGURATION; + if (!CONFIG_TEST_FLAG(flag, PARTIAL_CONFIG)) { bridge_disable = true; } @@ -212,6 +225,7 @@ static int intel_fpga_config_start(uint32_t flag) if (CONFIG_TEST_FLAG(flag, AUTHENTICATION)) { size = 1; bridge_disable = false; + request_type = BITSTREAM_AUTH; } mailbox_clear_response(); @@ -224,6 +238,7 @@ static int intel_fpga_config_start(uint32_t flag) if (status < 0) { bridge_disable = false; + request_type = NO_REQUEST; return INTEL_SIP_SMC_STATUS_ERROR; } @@ -644,7 +659,7 @@ uintptr_t sip_smc_handler_v1(uint32_t smc_fid, SMC_UUID_RET(handle, intl_svc_uid); case INTEL_SIP_SMC_FPGA_CONFIG_ISDONE: - status = intel_mailbox_fpga_config_isdone(x1); + status = intel_mailbox_fpga_config_isdone(); SMC_RET4(handle, status, 0, 0, 0); case INTEL_SIP_SMC_FPGA_CONFIG_GET_MEM: diff --git a/plat/intel/soc/stratix10/include/s10_noc.h b/plat/intel/soc/stratix10/include/s10_noc.h deleted file mode 100644 index 3e1e52719..000000000 --- a/plat/intel/soc/stratix10/include/s10_noc.h +++ /dev/null @@ -1,63 +0,0 @@ -/* - * Copyright (c) 2019, Intel Corporation. All rights reserved. - * - * SPDX-License-Identifier: BSD-3-Clause - */ - -#define AXI_AP (1<<0) -#define FPGA2SOC (1<<16) -#define MPU (1<<24) -#define S10_NOC_PER_SCR_NAND 0xffd21000 -#define S10_NOC_PER_SCR_NAND_DATA 0xffd21004 -#define S10_NOC_PER_SCR_USB0 0xffd2100c -#define S10_NOC_PER_SCR_USB1 0xffd21010 -#define S10_NOC_PER_SCR_SPI_M0 0xffd2101c -#define S10_NOC_PER_SCR_SPI_M1 0xffd21020 -#define S10_NOC_PER_SCR_SPI_S0 0xffd21024 -#define S10_NOC_PER_SCR_SPI_S1 0xffd21028 -#define S10_NOC_PER_SCR_EMAC0 0xffd2102c -#define S10_NOC_PER_SCR_EMAC1 0xffd21030 -#define S10_NOC_PER_SCR_EMAC2 0xffd21034 -#define S10_NOC_PER_SCR_SDMMC 0xffd21040 -#define S10_NOC_PER_SCR_GPIO0 0xffd21044 -#define S10_NOC_PER_SCR_GPIO1 0xffd21048 -#define S10_NOC_PER_SCR_I2C0 0xffd21050 -#define S10_NOC_PER_SCR_I2C1 0xffd21058 -#define S10_NOC_PER_SCR_I2C2 0xffd2105c -#define S10_NOC_PER_SCR_I2C3 0xffd21060 -#define S10_NOC_PER_SCR_SP_TIMER0 0xffd21064 -#define S10_NOC_PER_SCR_SP_TIMER1 0xffd21068 -#define S10_NOC_PER_SCR_UART0 0xffd2106c -#define S10_NOC_PER_SCR_UART1 0xffd21070 - - -#define S10_NOC_SYS_SCR_DMA_ECC 0xffd21108 -#define S10_NOC_SYS_SCR_EMAC0RX_ECC 0xffd2110c -#define S10_NOC_SYS_SCR_EMAC0TX_ECC 0xffd21110 -#define S10_NOC_SYS_SCR_EMAC1RX_ECC 0xffd21114 -#define S10_NOC_SYS_SCR_EMAC1TX_ECC 0xffd21118 -#define S10_NOC_SYS_SCR_EMAC2RX_ECC 0xffd2111c -#define S10_NOC_SYS_SCR_EMAC2TX_ECC 0xffd21120 -#define S10_NOC_SYS_SCR_NAND_ECC 0xffd2112c -#define S10_NOC_SYS_SCR_NAND_READ_ECC 0xffd21130 -#define S10_NOC_SYS_SCR_NAND_WRITE_ECC 0xffd21134 -#define S10_NOC_SYS_SCR_OCRAM_ECC 0xffd21138 -#define S10_NOC_SYS_SCR_SDMMC_ECC 0xffd21140 -#define S10_NOC_SYS_SCR_USB0_ECC 0xffd21144 -#define S10_NOC_SYS_SCR_USB1_ECC 0xffd21148 -#define S10_NOC_SYS_SCR_CLK_MGR 0xffd2114c -#define S10_NOC_SYS_SCR_IO_MGR 0xffd21154 -#define S10_NOC_SYS_SCR_RST_MGR 0xffd21158 -#define S10_NOC_SYS_SCR_SYS_MGR 0xffd2115c -#define S10_NOC_SYS_SCR_OSC0_TIMER 0xffd21160 -#define S10_NOC_SYS_SCR_OSC1_TIMER 0xffd21164 -#define S10_NOC_SYS_SCR_WATCHDOG0 0xffd21168 -#define S10_NOC_SYS_SCR_WATCHDOG1 0xffd2116c -#define S10_NOC_SYS_SCR_WATCHDOG2 0xffd21170 -#define S10_NOC_SYS_SCR_WATCHDOG3 0xffd21174 -#define S10_NOC_SYS_SCR_DAP 0xffd21178 -#define S10_NOC_SYS_SCR_L4_NOC_PROBES 0xffd21190 -#define S10_NOC_SYS_SCR_L4_NOC_QOS 0xffd21194 - -#define S10_CCU_NOC_BRIDGE_CPU0_RAM 0xf7004688 -#define S10_CCU_NOC_BRIDGE_IOM_RAM 0xf7004688