Add Makalu CPU lib
Add basic support for Makalu CPU. Signed-off-by: John Powell <john.powell@arm.com> Change-Id: I4e85d425eedea499adf585eb8ab548931185043d
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#ifndef CORTEX_MAKALU_H
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#define CORTEX_MAKALU_H
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#define CORTEX_MAKALU_MIDR U(0x410FD4D0)
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/*******************************************************************************
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* CPU Extended Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_CPUECTLR_EL1 S3_0_C15_C1_4
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/*******************************************************************************
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* CPU Power Control register specific definitions
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******************************************************************************/
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#define CORTEX_MAKALU_CPUPWRCTLR_EL1 S3_0_C15_C2_7
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#define CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT U(1)
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#endif /* CORTEX_MAKALU_H */
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/*
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* Copyright (c) 2021, Arm Limited. All rights reserved.
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*
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* SPDX-License-Identifier: BSD-3-Clause
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*/
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#include <arch.h>
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#include <asm_macros.S>
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#include <common/bl_common.h>
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#include <cortex_makalu.h>
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#include <cpu_macros.S>
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#include <plat_macros.S>
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/* Hardware handled coherency */
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#if HW_ASSISTED_COHERENCY == 0
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#error "Cortex Makalu must be compiled with HW_ASSISTED_COHERENCY enabled"
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#endif
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/* 64-bit only core */
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#if CTX_INCLUDE_AARCH32_REGS == 1
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#error "Cortex Makalu supports only AArch64. Compile with CTX_INCLUDE_AARCH32_REGS=0"
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#endif
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func cortex_makalu_reset_func
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/* Disable speculative loads */
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msr SSBS, xzr
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isb
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ret
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endfunc cortex_makalu_reset_func
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/* ----------------------------------------------------
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* HW will do the cache maintenance while powering down
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* ----------------------------------------------------
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*/
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func cortex_makalu_core_pwr_dwn
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/* ---------------------------------------------------
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* Enable CPU power down bit in power control register
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* ---------------------------------------------------
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*/
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mrs x0, CORTEX_MAKALU_CPUPWRCTLR_EL1
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orr x0, x0, #CORTEX_MAKALU_CPUPWRCTLR_EL1_CORE_PWRDN_BIT
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msr CORTEX_MAKALU_CPUPWRCTLR_EL1, x0
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isb
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ret
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endfunc cortex_makalu_core_pwr_dwn
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#if REPORT_ERRATA
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/*
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* Errata printing function for Cortex Makalu. Must follow AAPCS.
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*/
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func cortex_makalu_errata_report
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ret
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endfunc cortex_makalu_errata_report
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#endif
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/* ---------------------------------------------
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* This function provides Cortex Makalu-specific
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* register information for crash reporting.
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* It needs to return with x6 pointing to
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* a list of register names in ascii and
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* x8 - x15 having values of registers to be
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* reported.
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* ---------------------------------------------
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*/
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.section .rodata.cortex_makalu_regs, "aS"
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cortex_makalu_regs: /* The ascii list of register names to be reported */
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.asciz "cpuectlr_el1", ""
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func cortex_makalu_cpu_reg_dump
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adr x6, cortex_makalu_regs
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mrs x8, CORTEX_MAKALU_CPUECTLR_EL1
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ret
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endfunc cortex_makalu_cpu_reg_dump
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declare_cpu_ops cortex_makalu, CORTEX_MAKALU_MIDR, \
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cortex_makalu_reset_func, \
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cortex_makalu_core_pwr_dwn
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2020, Arm Limited. All rights reserved.
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# Copyright (c) 2021, Arm Limited. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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@ -68,7 +68,8 @@ else
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65ae.S \
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_matterhorn.S
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lib/cpus/aarch64/cortex_matterhorn.S \
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lib/cpus/aarch64/cortex_makalu.S
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# AArch64/AArch32 cores
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FPGA_CPU_LIBS += lib/cpus/aarch64/cortex_a55.S \
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@ -1,5 +1,5 @@
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#
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# Copyright (c) 2013-2021, ARM Limited and Contributors. All rights reserved.
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# Copyright (c) 2013-2021, Arm Limited and Contributors. All rights reserved.
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#
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# SPDX-License-Identifier: BSD-3-Clause
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#
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lib/cpus/aarch64/cortex_a78_ae.S \
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lib/cpus/aarch64/cortex_klein.S \
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lib/cpus/aarch64/cortex_matterhorn.S \
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lib/cpus/aarch64/cortex_makalu.S \
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lib/cpus/aarch64/cortex_a65.S \
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lib/cpus/aarch64/cortex_a65ae.S
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endif
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