Tegra: memctrl_v2: platform handlers to program MSS
Introduce platform handlers to program the MSS settings. This allows the current driver to scale to future chips. Change-Id: I40a27648a1a3c73b1ce38dafddc1babb6f0b0d9b Signed-off-by: Puneet Saxena <puneets@nvidia.com> Signed-off-by: Krishna Reddy <vdumpa@nvidia.com>
This commit is contained in:
Puneet Saxena
Varun Wadekar
parent
ae478c26e5
commit
ab2eb455d6
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@ -25,318 +25,6 @@
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static uint64_t video_mem_base;
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static uint64_t video_mem_size_mb;
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static void tegra_memctrl_reconfig_mss_clients(void)
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{
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#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
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uint32_t val, wdata_0, wdata_1;
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/*
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* Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
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* boot and strongly ordered MSS clients to flush existing memory
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* traffic and stall future requests.
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*/
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
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assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
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#if ENABLE_AFI_DEVICE
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MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
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#endif
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MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
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} while ((val & wdata_0) != wdata_0);
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
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assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
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wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
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MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
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tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
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/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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/* Wait one more time due to SW WAR for known legacy issue */
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do {
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
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} while ((val & wdata_1) != wdata_1);
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/*
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* Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
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* strongly ordered MSS clients. ROC needs to be single point
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* of control on overriding the memory type. So, remove TSA's
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* memtype override.
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*
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* MC clients with default SO_DEV override still enabled at TSA:
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* AONW, BPMPW, SCEW, APEW
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*/
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#if ENABLE_AFI_DEVICE
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mc_set_tsa_passthrough(AFIW);
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#endif
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mc_set_tsa_passthrough(HDAW);
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mc_set_tsa_passthrough(SATAW);
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mc_set_tsa_passthrough(XUSB_HOSTW);
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mc_set_tsa_passthrough(XUSB_DEVW);
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mc_set_tsa_passthrough(SDMMCWAB);
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mc_set_tsa_passthrough(APEDMAW);
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mc_set_tsa_passthrough(SESWR);
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mc_set_tsa_passthrough(ETRW);
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mc_set_tsa_passthrough(AXISW);
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mc_set_tsa_passthrough(EQOSW);
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mc_set_tsa_passthrough(UFSHCW);
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mc_set_tsa_passthrough(BPMPDMAW);
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mc_set_tsa_passthrough(AONDMAW);
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mc_set_tsa_passthrough(SCEDMAW);
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/* Parker has no IO Coherency support and need the following:
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* Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
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* ISO clients(DISP, VI, EQOS) should never snoop caches and
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* don't need ROC/PCFIFO ordering.
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* ISO clients(EQOS) that need ordering should use PCFIFO ordering
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* and bypass ROC ordering by using FORCE_NON_COHERENT path.
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* FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
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* over SMMU attributes.
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* Force all Normal memory transactions from ISO and non-ISO to be
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* non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
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* Force the SO_DEV transactions from ordered ISO clients(EQOS) to
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* non-coherent path and enable MC PCFIFO interlock for ordering.
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* Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
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* XUSB, SATA) to coherent so that the transactions are
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* ordered by ROC.
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* PCFIFO ensure write ordering.
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* Read after Write ordering is maintained/enforced by MC clients.
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* Clients that need PCIe type write ordering must
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* go through ROC ordering.
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* Ordering enable for Read clients is not necessary.
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* R5's and A9 would get necessary ordering from AXI and
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* don't need ROC ordering enable:
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* - MMIO ordering is through dev mapping and MMIO
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* accesses bypass SMMU.
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* - Normal memory is accessed through SMMU and ordering is
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* ensured by client and AXI.
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* - Ack point for Normal memory is WCAM in MC.
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* - MMIO's can be early acked and AXI ensures dev memory ordering,
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* Client ensures read/write direction change ordering.
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* - See Bug 200312466 for more details.
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*
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* CGID_TAG_ADR is only present from T186 A02. As this code is common
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* between A01 and A02, tegra_memctrl_set_overrides() programs
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* CGID_TAG_ADR for the necessary clients on A02.
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*/
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mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
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mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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/* See bug 200131110 comment #35*/
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mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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/* See bug 200131110 comment #35*/
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mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
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mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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/* See bug 200131110 comment #35 */
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mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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/*
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* See bug 200131110 comment #35 - there are no normal requests
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* and AWID for SO/DEV requests is hardcoded in RTL for a
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* particular PCIE controller
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*/
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mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
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mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
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/*
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* At this point, ordering can occur at ROC. So, remove PCFIFO's
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* control over ordering requests.
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*
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* Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
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* boot and strongly ordered MSS clients
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*/
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val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
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#if ENABLE_AFI_DEVICE
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mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
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#endif
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mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
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mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
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val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
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mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
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val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
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val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
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mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
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mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
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/* EQOSW is the only client that has PCFIFO order enabled. */
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val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
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val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
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mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
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tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
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/*
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* Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
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* clients to allow memory traffic from all clients to start passing
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* through ROC
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*/
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val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
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assert(val == wdata_0);
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wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
|
||||
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
|
||||
assert(val == wdata_1);
|
||||
|
||||
wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static void tegra_memctrl_set_overrides(void)
|
||||
{
|
||||
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
|
||||
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
|
||||
uint32_t num_txn_override_cfgs;
|
||||
uint32_t i, val;
|
||||
|
||||
/* Get the settings from the platform */
|
||||
assert(plat_mc_settings != NULL);
|
||||
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
|
||||
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
|
||||
|
||||
/*
|
||||
* Set the MC_TXN_OVERRIDE registers for write clients.
|
||||
*/
|
||||
if ((tegra_chipid_is_t186()) &&
|
||||
(!tegra_platform_is_silicon() ||
|
||||
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
|
||||
|
||||
/*
|
||||
* GPU and NVENC settings for Tegra186 simulation and
|
||||
* Silicon rev. A01
|
||||
*/
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
|
||||
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
|
||||
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
|
||||
|
||||
} else {
|
||||
|
||||
/*
|
||||
* Settings for Tegra186 silicon rev. A02 and onwards.
|
||||
*/
|
||||
for (i = 0; i < num_txn_override_cfgs; i++) {
|
||||
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
|
||||
val | mc_txn_override_cfgs[i].cgid_tag);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
* Init Memory controller during boot.
|
||||
*/
|
||||
|
|
@ -398,10 +86,14 @@ void tegra_memctrl_setup(void)
|
|||
* boots with MSS having all control, but ROC provides a performance
|
||||
* boost as compared to MSS.
|
||||
*/
|
||||
tegra_memctrl_reconfig_mss_clients();
|
||||
if (plat_mc_settings->reconfig_mss_clients != NULL) {
|
||||
plat_mc_settings->reconfig_mss_clients();
|
||||
}
|
||||
|
||||
/* Program overrides for MC transactions */
|
||||
tegra_memctrl_set_overrides();
|
||||
if (plat_mc_settings->set_txn_overrides != NULL) {
|
||||
plat_mc_settings->set_txn_overrides();
|
||||
}
|
||||
}
|
||||
|
||||
/*
|
||||
|
|
@ -409,16 +101,24 @@ void tegra_memctrl_setup(void)
|
|||
*/
|
||||
void tegra_memctrl_restore_settings(void)
|
||||
{
|
||||
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
|
||||
|
||||
assert(plat_mc_settings != NULL);
|
||||
|
||||
/*
|
||||
* Re-configure MSS to allow ROC to deal with ordering of the
|
||||
* Memory Controller traffic. This is needed as the Memory Controller
|
||||
* resets during System Suspend with MSS having all control, but ROC
|
||||
* provides a performance boost as compared to MSS.
|
||||
*/
|
||||
tegra_memctrl_reconfig_mss_clients();
|
||||
if (plat_mc_settings->reconfig_mss_clients != NULL) {
|
||||
plat_mc_settings->reconfig_mss_clients();
|
||||
}
|
||||
|
||||
/* Program overrides for MC transactions */
|
||||
tegra_memctrl_set_overrides();
|
||||
if (plat_mc_settings->set_txn_overrides != NULL) {
|
||||
plat_mc_settings->set_txn_overrides();
|
||||
}
|
||||
|
||||
/* video memory carveout region */
|
||||
if (video_mem_base != 0ULL) {
|
||||
|
|
|
|||
|
|
@ -11,184 +11,9 @@
|
|||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <mmio.h>
|
||||
#include <stdint.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* StreamID to indicate no SMMU translations (requests to be steered on the
|
||||
* SMMU bypass path)
|
||||
******************************************************************************/
|
||||
#define MC_STREAM_ID_MAX 0x7FU
|
||||
|
||||
/*******************************************************************************
|
||||
* Stream ID Override Config registers
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro to calculate Security cfg register addr from StreamID Override register
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller transaction override config registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
|
||||
|
||||
/*******************************************************************************
|
||||
* Structure to hold the transaction override settings to use to override
|
||||
* client inputs
|
||||
|
|
@ -229,6 +54,25 @@ typedef struct mc_streamid_security_cfg {
|
|||
#define CLIENT_FLAG_NON_SECURE 1U
|
||||
#define CLIENT_INPUTS_OVERRIDE 1U
|
||||
#define CLIENT_INPUTS_NO_OVERRIDE 0U
|
||||
/*******************************************************************************
|
||||
* StreamID to indicate no SMMU translations (requests to be steered on the
|
||||
* SMMU bypass path)
|
||||
******************************************************************************/
|
||||
#define MC_STREAM_ID_MAX 0x7FU
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller SMMU Bypass config register
|
||||
******************************************************************************/
|
||||
#define MC_SMMU_BYPASS_CONFIG 0x1820U
|
||||
#define MC_SMMU_BYPASS_CTRL_MASK 0x3U
|
||||
#define MC_SMMU_BYPASS_CTRL_SHIFT 0U
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
|
||||
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
|
||||
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
|
||||
|
||||
#define mc_make_sec_cfg(off, ns, ovrrd, access) \
|
||||
{ \
|
||||
|
|
@ -250,131 +94,10 @@ typedef struct tegra_mc_settings {
|
|||
uint32_t num_streamid_security_cfgs;
|
||||
const mc_txn_override_cfg_t *txn_override_cfg;
|
||||
uint32_t num_txn_override_cfgs;
|
||||
void (*reconfig_mss_clients)(void);
|
||||
void (*set_txn_overrides)(void);
|
||||
} tegra_mc_settings_t;
|
||||
|
||||
#endif /* __ASSEMBLY__ */
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller SMMU Bypass config register
|
||||
******************************************************************************/
|
||||
#define MC_SMMU_BYPASS_CONFIG 0x1820U
|
||||
#define MC_SMMU_BYPASS_CTRL_MASK 0x3U
|
||||
#define MC_SMMU_BYPASS_CTRL_SHIFT 0U
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_ALL (0U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_RSVD (1U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID (2U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_CTRL_TBU_BYPASS_NONE (3U << MC_SMMU_BYPASS_CTRL_SHIFT)
|
||||
#define MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT (1U << 31)
|
||||
#define MC_SMMU_BYPASS_CONFIG_SETTINGS (MC_SMMU_BYPASS_CONFIG_WRITE_ACCESS_BIT | \
|
||||
MC_SMMU_CTRL_TBU_BYPASS_SPL_STREAMID)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
|
||||
* MC_TXN_OVERRIDE_CONFIG_{module} registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3U
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller Reset Control registers
|
||||
******************************************************************************/
|
||||
#define MC_CLIENT_HOTRESET_CTRL0 0x200U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller's PCFIFO client configuration registers
|
||||
******************************************************************************/
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0UL << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1UL << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0UL << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1UL << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0UL << 29)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1UL << 29)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0UL << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1UL << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0UL << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1UL << 13)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddcUL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0UL << 7)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1UL << 7)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0UL << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1UL << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0UL << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1UL << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0UL << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1UL << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0UL << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1UL << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1UL << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0UL << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1UL << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0UL << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1UL << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0UL << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1UL << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0UL << 30)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1UL << 30)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0UL
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0UL << 0)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1UL << 0)
|
||||
|
||||
#ifndef __ASSEMBLY__
|
||||
|
||||
#include <lib/mmio.h>
|
||||
|
||||
static inline uint32_t tegra_mc_read_32(uint32_t off)
|
||||
{
|
||||
return mmio_read_32(TEGRA_MC_BASE + off);
|
||||
|
|
@ -410,6 +133,22 @@ static inline void tegra_mc_streamid_write_32(uint32_t off, uint32_t val)
|
|||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
}
|
||||
|
||||
#define mc_set_tsa_w_passthrough(client) \
|
||||
{ \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSW_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSW_RESET_W & \
|
||||
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
}
|
||||
|
||||
#define mc_set_tsa_r_passthrough(client) \
|
||||
{ \
|
||||
mmio_write_32(TEGRA_TSA_BASE + TSA_CONFIG_STATIC0_CSR_##client, \
|
||||
(TSA_CONFIG_STATIC0_CSR_RESET_R & \
|
||||
(uint32_t)~TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_MASK) | \
|
||||
(uint32_t)TSA_CONFIG_CSW_MEMTYPE_OVERRIDE_PASTHRU); \
|
||||
}
|
||||
|
||||
#define mc_set_txn_override(client, normal_axi_id, so_dev_axi_id, normal_override, so_dev_override) \
|
||||
{ \
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_##client, \
|
||||
|
|
|
|||
|
|
@ -0,0 +1,285 @@
|
|||
/*
|
||||
* Copyright (c) 2017, NVIDIA CORPORATION. All rights reserved.
|
||||
*
|
||||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#ifndef TEGRA_MC_DEF_H
|
||||
#define TEGRA_MC_DEF_H
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller's PCFIFO client configuration registers
|
||||
******************************************************************************/
|
||||
#define MC_PCFIFO_CLIENT_CONFIG0 0xdd0U
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1 0xdd4U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL 0x20000U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_UNORDERED (0U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_AFIW_MASK (1U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_UNORDERED (0U << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_HDAW_MASK (1U << 21)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_UNORDERED (0U << 29)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG1_PCFIFO_SATAW_MASK (1U << 29)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2 0xdd8U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL 0x20000U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_UNORDERED (0U << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_HOSTW_MASK (1U << 11)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_UNORDERED (0U << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG2_PCFIFO_XUSB_DEVW_MASK (1U << 13)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3 0xddcU
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_UNORDERED (0U << 7)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG3_PCFIFO_SDMMCWAB_MASK (1U << 7)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4 0xde0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_UNORDERED (0U << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SESWR_MASK (1U << 1)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_UNORDERED (0U << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_ETRW_MASK (1U << 5)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_UNORDERED (0U << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AXISW_MASK (1U << 13)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_UNORDERED (0U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_ORDERED (1U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_EQOSW_MASK (1U << 15)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_UNORDERED (0U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_UFSHCW_MASK (1U << 17)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_UNORDERED (0U << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_BPMPDMAW_MASK (1U << 22)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_UNORDERED (0U << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_AONDMAW_MASK (1U << 26)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_UNORDERED (0U << 30)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG4_PCFIFO_SCEDMAW_MASK (1U << 30)
|
||||
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5 0xbf4U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL 0U
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_UNORDERED (0U << 0)
|
||||
#define MC_PCFIFO_CLIENT_CONFIG5_PCFIFO_APEDMAW_MASK (1U << 0)
|
||||
|
||||
/*******************************************************************************
|
||||
* Stream ID Override Config registers
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_CFG_PTCR 0x000U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIR 0x070U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAR 0x0A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HOST1XDMAR 0x0B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSRD 0x0E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAR 0x0F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCORER 0x138U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVENCSWR 0x158U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AFIW 0x188U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_HDAW 0x1A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_MPCOREW 0x1C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SATAW 0x1E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPRA 0x220U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWA 0x230U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ISPWB 0x238U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTR 0x250U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_HOSTW 0x258U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVR 0x260U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_XUSB_DEVW 0x268U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRD 0x2A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWR 0x2A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD 0x2C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR 0x2C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRA 0x300U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAA 0x308U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCR 0x310U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCRAB 0x318U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWA 0x320U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAA 0x328U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCW 0x330U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SDMMCWAB 0x338U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD 0x360U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSWR 0x368U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VIW 0x390U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD 0x3C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSWR 0x3C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APER 0x3D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEW 0x3D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSRD 0x3F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVJPGSWR 0x3F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESRD 0x400U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SESWR 0x408U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRR 0x420U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_ETRW 0x428U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSRDB 0x430U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_TSECSWRB 0x438U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSRD2 0x440U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_GPUSWR2 0x448U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISR 0x460U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AXISW 0x468U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSR 0x470U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_EQOSW 0x478U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCR 0x480U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_UFSHCW 0x488U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR 0x490U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPR 0x498U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPW 0x4A0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAR 0x4A8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_BPMPDMAW 0x4B0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONR 0x4B8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONW 0x4C0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAR 0x4C8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_AONDMAW 0x4D0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCER 0x4D8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEW 0x4E0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAR 0x4E8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_SCEDMAW 0x4F0U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAR 0x4F8U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_APEDMAW 0x500U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDISPLAYR1 0x508U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_VICSRD1 0x510U
|
||||
#define MC_STREAMID_OVERRIDE_CFG_NVDECSRD1 0x518U
|
||||
|
||||
/*******************************************************************************
|
||||
* Macro to calculate Security cfg register addr from StreamID Override register
|
||||
******************************************************************************/
|
||||
#define MC_STREAMID_OVERRIDE_TO_SECURITY_CFG(addr) ((addr) + (uint32_t)sizeof(uint32_t))
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_SO_DEV (0U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_SO_DEV (1U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_SO_DEV (3U << 4)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_NO_OVERRIDE_NORMAL (0U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_NON_COHERENT_NORMAL (1U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_NORMAL (2U << 8)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_FORCE_COHERENT_SNOOP_NORMAL (3U << 8)
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_ZERO (0U << 12)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_CGID_SO_DEV_CLIENT_AXI_ID (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller transaction override config registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAR 0x10a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPW 0x14a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_PTCR 0x1000U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR 0x1490U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSW 0x1478U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSWR 0x13f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPRA 0x1220U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAA 0x1328U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD 0x1360U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCOREW 0x11c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD 0x12c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISR 0x1460U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAW 0x14f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCW 0x1330U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_EQOSR 0x1470U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAR 0x14f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSRD 0x10e0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAB 0x1318U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSRD1 0x1510U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAR 0x14a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VIW 0x1390U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRAA 0x1308U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXISW 0x1468U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVR 0x1260U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCR 0x1480U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWR 0x12a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR 0x12c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAR 0x10f8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTW 0x1258U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSWRB 0x1438U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSRD2 0x1440U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEDMAR 0x14e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_GPUSWR2 0x1448U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAW 0x14d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEDMAW 0x1500U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONW 0x14c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HOST1XDMAR 0x10b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRR 0x1420U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESWR 0x1408U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVJPGSRD 0x13f0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD 0x13c0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRDB 0x1430U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPDMAW 0x14b0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APER 0x13d0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSRD1 0x1518U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_HOSTR 0x1250U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWA 0x1230U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SESRD 0x1400U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCER 0x14d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONR 0x14b8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_MPCORER 0x1138U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWA 0x1320U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_HDAW 0x11a8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDECSWR 0x13c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_UFSHCW 0x1488U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AONDMAR 0x14c8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SATAW 0x11e8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ETRW 0x1428U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_VICSWR 0x1368U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVENCSWR 0x1158U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIR 0x1070U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCWAB 0x1338U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCRA 0x1300U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_NVDISPLAYR1 0x1508U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_ISPWB 0x1238U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_BPMPR 0x1498U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_APEW 0x13d8U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SDMMCR 0x1310U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_XUSB_DEVW 0x1268U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_TSECSRD 0x12a0U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AFIW 0x1188U
|
||||
#define MC_TXN_OVERRIDE_CONFIG_SCEW 0x14e0U
|
||||
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_CGID (1U << 0)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_COH_PATH_OVERRIDE_SO_DEV (2U << 4)
|
||||
#define MC_TXN_OVERRIDE_CONFIG_AXID_OVERRIDE_SO_DEV_CGID_SO_DEV_CLIENT (1U << 12)
|
||||
|
||||
/*******************************************************************************
|
||||
* Non-SO_DEV transactions override values for CGID_TAG bitfield for the
|
||||
* MC_TXN_OVERRIDE_CONFIG_{module} registers
|
||||
******************************************************************************/
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_DEFAULT 0U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID 1U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ZERO 2U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_ADR 3U
|
||||
#define MC_TXN_OVERRIDE_CGID_TAG_MASK 3ULL
|
||||
|
||||
/*******************************************************************************
|
||||
* Memory Controller Reset Control registers
|
||||
******************************************************************************/
|
||||
#define MC_CLIENT_HOTRESET_CTRL0 0x200U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HC_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_ISP2_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_MPCORE_FLUSH_ENB (1U << 9)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_NVENC_FLUSH_ENB (1U << 11)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB (1U << 15)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VI_FLUSH_ENB (1U << 17)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_VIC_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_TSEC_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC1A_FLUSH_ENB (1U << 29)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC2A_FLUSH_ENB (1U << 30)
|
||||
#define MC_CLIENT_HOTRESET_CTRL0_SDMMC3A_FLUSH_ENB (1U << 31)
|
||||
#define MC_CLIENT_HOTRESET_STATUS0 0x204U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1 0x970U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_RESET_VAL 0U
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB (1U << 0)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_GPU_FLUSH_ENB (1U << 2)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDEC_FLUSH_ENB (1U << 5)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB (1U << 6)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB (1U << 7)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVJPG_FLUSH_ENB (1U << 8)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB (1U << 12)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_TSECB_FLUSH_ENB (1U << 13)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB (1U << 18)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB (1U << 19)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB (1U << 20)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_NVDISPLAY_FLUSH_ENB (1U << 21)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB (1U << 22)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB (1U << 23)
|
||||
#define MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB (1U << 24)
|
||||
#define MC_CLIENT_HOTRESET_STATUS1 0x974U
|
||||
|
||||
#endif /* TEGRA_MC_DEF_H */
|
||||
|
|
@ -4,9 +4,12 @@
|
|||
* SPDX-License-Identifier: BSD-3-Clause
|
||||
*/
|
||||
|
||||
#include <assert.h>
|
||||
#include <common/bl_common.h>
|
||||
|
||||
#include <memctrl_v2.h>
|
||||
#include <tegra_mc_def.h>
|
||||
#include <tegra_platform.h>
|
||||
|
||||
/*******************************************************************************
|
||||
* Array to hold stream_id override config register offsets
|
||||
|
|
@ -201,6 +204,318 @@ const static mc_txn_override_cfg_t tegra186_txn_override_cfgs[] = {
|
|||
mc_make_txn_override_cfg(SCEW, CGID_TAG_ADR),
|
||||
};
|
||||
|
||||
static void tegra186_memctrl_reconfig_mss_clients(void)
|
||||
{
|
||||
#if ENABLE_ROC_FOR_ORDERING_CLIENT_REQUESTS
|
||||
uint32_t val, wdata_0, wdata_1;
|
||||
|
||||
/*
|
||||
* Assert Memory Controller's HOTRESET_FLUSH_ENABLE signal for
|
||||
* boot and strongly ordered MSS clients to flush existing memory
|
||||
* traffic and stall future requests.
|
||||
*/
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
|
||||
assert(val == MC_CLIENT_HOTRESET_CTRL0_RESET_VAL);
|
||||
|
||||
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_HDA_FLUSH_ENB |
|
||||
#if ENABLE_AFI_DEVICE
|
||||
MC_CLIENT_HOTRESET_CTRL0_AFI_FLUSH_ENB |
|
||||
#endif
|
||||
MC_CLIENT_HOTRESET_CTRL0_SATA_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL0_XUSB_HOST_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL0_XUSB_DEV_FLUSH_ENB;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
|
||||
|
||||
/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
|
||||
do {
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
|
||||
} while ((val & wdata_0) != wdata_0);
|
||||
|
||||
/* Wait one more time due to SW WAR for known legacy issue */
|
||||
do {
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS0);
|
||||
} while ((val & wdata_0) != wdata_0);
|
||||
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
|
||||
assert(val == MC_CLIENT_HOTRESET_CTRL1_RESET_VAL);
|
||||
|
||||
wdata_1 = MC_CLIENT_HOTRESET_CTRL1_SDMMC4A_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_APE_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_SE_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_ETR_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_AXIS_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_EQOS_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_UFSHC_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_BPMP_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_AON_FLUSH_ENB |
|
||||
MC_CLIENT_HOTRESET_CTRL1_SCE_FLUSH_ENB;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
|
||||
|
||||
/* Wait for HOTRESET STATUS to indicate FLUSH_DONE */
|
||||
do {
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
|
||||
} while ((val & wdata_1) != wdata_1);
|
||||
|
||||
/* Wait one more time due to SW WAR for known legacy issue */
|
||||
do {
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_STATUS1);
|
||||
} while ((val & wdata_1) != wdata_1);
|
||||
|
||||
/*
|
||||
* Change MEMTYPE_OVERRIDE from SO_DEV -> PASSTHRU for boot and
|
||||
* strongly ordered MSS clients. ROC needs to be single point
|
||||
* of control on overriding the memory type. So, remove TSA's
|
||||
* memtype override.
|
||||
*
|
||||
* MC clients with default SO_DEV override still enabled at TSA:
|
||||
* AONW, BPMPW, SCEW, APEW
|
||||
*/
|
||||
#if ENABLE_AFI_DEVICE
|
||||
mc_set_tsa_passthrough(AFIW);
|
||||
#endif
|
||||
mc_set_tsa_passthrough(HDAW);
|
||||
mc_set_tsa_passthrough(SATAW);
|
||||
mc_set_tsa_passthrough(XUSB_HOSTW);
|
||||
mc_set_tsa_passthrough(XUSB_DEVW);
|
||||
mc_set_tsa_passthrough(SDMMCWAB);
|
||||
mc_set_tsa_passthrough(APEDMAW);
|
||||
mc_set_tsa_passthrough(SESWR);
|
||||
mc_set_tsa_passthrough(ETRW);
|
||||
mc_set_tsa_passthrough(AXISW);
|
||||
mc_set_tsa_passthrough(EQOSW);
|
||||
mc_set_tsa_passthrough(UFSHCW);
|
||||
mc_set_tsa_passthrough(BPMPDMAW);
|
||||
mc_set_tsa_passthrough(AONDMAW);
|
||||
mc_set_tsa_passthrough(SCEDMAW);
|
||||
|
||||
/* Parker has no IO Coherency support and need the following:
|
||||
* Ordered MC Clients on Parker are AFI, EQOS, SATA, XUSB.
|
||||
* ISO clients(DISP, VI, EQOS) should never snoop caches and
|
||||
* don't need ROC/PCFIFO ordering.
|
||||
* ISO clients(EQOS) that need ordering should use PCFIFO ordering
|
||||
* and bypass ROC ordering by using FORCE_NON_COHERENT path.
|
||||
* FORCE_NON_COHERENT/FORCE_COHERENT config take precedence
|
||||
* over SMMU attributes.
|
||||
* Force all Normal memory transactions from ISO and non-ISO to be
|
||||
* non-coherent(bypass ROC, avoid cache snoop to avoid perf hit).
|
||||
* Force the SO_DEV transactions from ordered ISO clients(EQOS) to
|
||||
* non-coherent path and enable MC PCFIFO interlock for ordering.
|
||||
* Force the SO_DEV transactions from ordered non-ISO clients (PCIe,
|
||||
* XUSB, SATA) to coherent so that the transactions are
|
||||
* ordered by ROC.
|
||||
* PCFIFO ensure write ordering.
|
||||
* Read after Write ordering is maintained/enforced by MC clients.
|
||||
* Clients that need PCIe type write ordering must
|
||||
* go through ROC ordering.
|
||||
* Ordering enable for Read clients is not necessary.
|
||||
* R5's and A9 would get necessary ordering from AXI and
|
||||
* don't need ROC ordering enable:
|
||||
* - MMIO ordering is through dev mapping and MMIO
|
||||
* accesses bypass SMMU.
|
||||
* - Normal memory is accessed through SMMU and ordering is
|
||||
* ensured by client and AXI.
|
||||
* - Ack point for Normal memory is WCAM in MC.
|
||||
* - MMIO's can be early acked and AXI ensures dev memory ordering,
|
||||
* Client ensures read/write direction change ordering.
|
||||
* - See Bug 200312466 for more details.
|
||||
*
|
||||
* CGID_TAG_ADR is only present from T186 A02. As this code is common
|
||||
* between A01 and A02, tegra_memctrl_set_overrides() programs
|
||||
* CGID_TAG_ADR for the necessary clients on A02.
|
||||
*/
|
||||
mc_set_txn_override(HDAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(BPMPW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(PTCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVDISPLAYR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(EQOSW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVJPGSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ISPRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCWAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(VICSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(MPCOREW, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(GPUSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AXISR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SCEDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(EQOSR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
/* See bug 200131110 comment #35*/
|
||||
mc_set_txn_override(APEDMAR, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVENCSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCRAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(VICSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(BPMPDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(VIW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCRAA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AXISW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(XUSB_DEVR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(UFSHCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(TSECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(GPUSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SATAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(XUSB_HOSTW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(TSECSWRB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(GPUSRD2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SCEDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(GPUSWR2, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AONDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
/* See bug 200131110 comment #35*/
|
||||
mc_set_txn_override(APEDMAW, CGID_TAG_CLIENT_AXI_ID, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AONW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(HOST1XDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ETRR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SESWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVJPGSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVDECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(TSECSRDB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(BPMPDMAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(APER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVDECSRD1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(XUSB_HOSTR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ISPWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SESRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SCER, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AONR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(MPCORER, CGID_TAG_DEFAULT, SO_DEV_ZERO, NO_OVERRIDE, NO_OVERRIDE);
|
||||
mc_set_txn_override(SDMMCWA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(HDAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVDECSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(UFSHCW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(AONDMAR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SATAW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(ETRW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(VICSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVENCSWR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
/* See bug 200131110 comment #35 */
|
||||
mc_set_txn_override(AFIR, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCWAB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCRA, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(NVDISPLAYR1, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(ISPWB, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(BPMPR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(APEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(SDMMCR, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
mc_set_txn_override(XUSB_DEVW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(TSECSRD, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
/*
|
||||
* See bug 200131110 comment #35 - there are no normal requests
|
||||
* and AWID for SO/DEV requests is hardcoded in RTL for a
|
||||
* particular PCIE controller
|
||||
*/
|
||||
mc_set_txn_override(AFIW, CGID_TAG_DEFAULT, SO_DEV_CLIENT_AXI_ID, FORCE_NON_COHERENT, FORCE_COHERENT);
|
||||
mc_set_txn_override(SCEW, CGID_TAG_DEFAULT, SO_DEV_ZERO, FORCE_NON_COHERENT, FORCE_NON_COHERENT);
|
||||
|
||||
/*
|
||||
* At this point, ordering can occur at ROC. So, remove PCFIFO's
|
||||
* control over ordering requests.
|
||||
*
|
||||
* Change PCFIFO_*_ORDERED_CLIENT from ORDERED -> UNORDERED for
|
||||
* boot and strongly ordered MSS clients
|
||||
*/
|
||||
val = MC_PCFIFO_CLIENT_CONFIG1_RESET_VAL &
|
||||
#if ENABLE_AFI_DEVICE
|
||||
mc_set_pcfifo_unordered_boot_so_mss(1, AFIW) &
|
||||
#endif
|
||||
mc_set_pcfifo_unordered_boot_so_mss(1, HDAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(1, SATAW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG1, val);
|
||||
|
||||
val = MC_PCFIFO_CLIENT_CONFIG2_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_HOSTW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(2, XUSB_DEVW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG2, val);
|
||||
|
||||
val = MC_PCFIFO_CLIENT_CONFIG3_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(3, SDMMCWAB);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG3, val);
|
||||
|
||||
val = MC_PCFIFO_CLIENT_CONFIG4_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SESWR) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, ETRW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AXISW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, UFSHCW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, BPMPDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, AONDMAW) &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(4, SCEDMAW);
|
||||
/* EQOSW is the only client that has PCFIFO order enabled. */
|
||||
val |= mc_set_pcfifo_ordered_boot_so_mss(4, EQOSW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG4, val);
|
||||
|
||||
val = MC_PCFIFO_CLIENT_CONFIG5_RESET_VAL &
|
||||
mc_set_pcfifo_unordered_boot_so_mss(5, APEDMAW);
|
||||
tegra_mc_write_32(MC_PCFIFO_CLIENT_CONFIG5, val);
|
||||
|
||||
/*
|
||||
* Deassert HOTRESET FLUSH_ENABLE for boot and strongly ordered MSS
|
||||
* clients to allow memory traffic from all clients to start passing
|
||||
* through ROC
|
||||
*/
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL0);
|
||||
assert(val == wdata_0);
|
||||
|
||||
wdata_0 = MC_CLIENT_HOTRESET_CTRL0_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL0, wdata_0);
|
||||
|
||||
val = tegra_mc_read_32(MC_CLIENT_HOTRESET_CTRL1);
|
||||
assert(val == wdata_1);
|
||||
|
||||
wdata_1 = MC_CLIENT_HOTRESET_CTRL1_RESET_VAL;
|
||||
tegra_mc_write_32(MC_CLIENT_HOTRESET_CTRL1, wdata_1);
|
||||
|
||||
#endif
|
||||
}
|
||||
|
||||
static void tegra186_memctrl_set_overrides(void)
|
||||
{
|
||||
const tegra_mc_settings_t *plat_mc_settings = tegra_get_mc_settings();
|
||||
const mc_txn_override_cfg_t *mc_txn_override_cfgs;
|
||||
uint32_t num_txn_override_cfgs;
|
||||
uint32_t i, val;
|
||||
|
||||
/* Get the settings from the platform */
|
||||
assert(plat_mc_settings != NULL);
|
||||
mc_txn_override_cfgs = plat_mc_settings->txn_override_cfg;
|
||||
num_txn_override_cfgs = plat_mc_settings->num_txn_override_cfgs;
|
||||
|
||||
/*
|
||||
* Set the MC_TXN_OVERRIDE registers for write clients.
|
||||
*/
|
||||
if ((tegra_chipid_is_t186()) &&
|
||||
(!tegra_platform_is_silicon() ||
|
||||
(tegra_platform_is_silicon() && (tegra_get_chipid_minor() == 1U)))) {
|
||||
|
||||
/*
|
||||
* GPU and NVENC settings for Tegra186 simulation and
|
||||
* Silicon rev. A01
|
||||
*/
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
|
||||
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR2,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_ZERO);
|
||||
|
||||
val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(MC_TXN_OVERRIDE_CONFIG_NVENCSWR,
|
||||
val | MC_TXN_OVERRIDE_CGID_TAG_CLIENT_AXI_ID);
|
||||
|
||||
} else {
|
||||
|
||||
/*
|
||||
* Settings for Tegra186 silicon rev. A02 and onwards.
|
||||
*/
|
||||
for (i = 0; i < num_txn_override_cfgs; i++) {
|
||||
val = tegra_mc_read_32(mc_txn_override_cfgs[i].offset);
|
||||
val &= (uint32_t)~MC_TXN_OVERRIDE_CGID_TAG_MASK;
|
||||
tegra_mc_write_32(mc_txn_override_cfgs[i].offset,
|
||||
val | mc_txn_override_cfgs[i].cgid_tag);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/*******************************************************************************
|
||||
* Struct to hold the memory controller settings
|
||||
******************************************************************************/
|
||||
|
|
@ -210,7 +525,9 @@ static tegra_mc_settings_t tegra186_mc_settings = {
|
|||
.streamid_security_cfg = tegra186_streamid_sec_cfgs,
|
||||
.num_streamid_security_cfgs = (uint32_t)ARRAY_SIZE(tegra186_streamid_sec_cfgs),
|
||||
.txn_override_cfg = tegra186_txn_override_cfgs,
|
||||
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs)
|
||||
.num_txn_override_cfgs = (uint32_t)ARRAY_SIZE(tegra186_txn_override_cfgs),
|
||||
.reconfig_mss_clients = tegra186_memctrl_reconfig_mss_clients,
|
||||
.set_txn_overrides = tegra186_memctrl_set_overrides,
|
||||
};
|
||||
|
||||
/*******************************************************************************
|
||||
|
|
|
|||
|
|
@ -8,6 +8,7 @@
|
|||
|
||||
#include <smmu.h>
|
||||
#include <tegra_def.h>
|
||||
#include <tegra_mc_def.h>
|
||||
|
||||
#define MAX_NUM_SMMU_DEVICES U(1)
|
||||
|
||||
|
|
|
|||
Loading…
Reference in New Issue