Merge pull request #388 from achingupta/ag/spd_suspend_levels_v3
Pass the target suspend level to SPD suspend hooks
This commit is contained in:
commit
ab434b0554
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@ -251,7 +251,7 @@ tsp_args_t *tsp_cpu_suspend_main(uint64_t arg0,
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* cpu's architectural state has been restored after wakeup from an earlier psci
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* cpu_suspend request.
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******************************************************************************/
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tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
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tsp_args_t *tsp_cpu_resume_main(uint64_t max_off_pwrlvl,
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uint64_t arg1,
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uint64_t arg2,
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uint64_t arg3,
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@ -272,8 +272,8 @@ tsp_args_t *tsp_cpu_resume_main(uint64_t suspend_level,
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#if LOG_LEVEL >= LOG_LEVEL_INFO
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spin_lock(&console_lock);
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INFO("TSP: cpu 0x%lx resumed. suspend level %ld\n",
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read_mpidr(), suspend_level);
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INFO("TSP: cpu 0x%lx resumed. maximum off power level %ld\n",
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read_mpidr(), max_off_pwrlvl);
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INFO("TSP: cpu 0x%lx: %d smcs, %d erets %d cpu suspend requests\n",
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read_mpidr(),
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tsp_stats[linear_id].smc_count,
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@ -286,9 +286,9 @@ typedef struct plat_psci_ops {
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typedef struct spd_pm_ops {
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void (*svc_on)(uint64_t target_cpu);
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int32_t (*svc_off)(uint64_t __unused);
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void (*svc_suspend)(uint64_t __unused);
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void (*svc_suspend)(uint64_t max_off_pwrlvl);
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void (*svc_on_finish)(uint64_t __unused);
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void (*svc_suspend_finish)(uint64_t suspend_level);
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void (*svc_suspend_finish)(uint64_t max_off_pwrlvl);
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int32_t (*svc_migrate)(uint64_t from_cpu, uint64_t to_cpu);
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int32_t (*svc_migrate_info)(uint64_t *resident_cpu);
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void (*svc_system_off)(void);
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@ -81,7 +81,7 @@ static int32_t opteed_cpu_off_handler(uint64_t unused)
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* This cpu is being suspended. S-EL1 state must have been saved in the
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* resident cpu (mpidr format) if it is a UP/UP migratable OPTEE.
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******************************************************************************/
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static void opteed_cpu_suspend_handler(uint64_t unused)
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static void opteed_cpu_suspend_handler(uint64_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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@ -147,7 +147,7 @@ static void opteed_cpu_on_finish_handler(uint64_t unused)
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* completed the preceding suspend call. Use that context to program an entry
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* into OPTEE to allow it to do any remaining book keeping
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******************************************************************************/
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static void opteed_cpu_suspend_finish_handler(uint64_t suspend_level)
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static void opteed_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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@ -156,10 +156,10 @@ static void opteed_cpu_suspend_finish_handler(uint64_t suspend_level)
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assert(optee_vectors);
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assert(get_optee_pstate(optee_ctx->state) == OPTEE_PSTATE_SUSPEND);
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/* Program the entry point, suspend_level and enter the SP */
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/* Program the entry point, max_off_pwrlvl and enter the SP */
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write_ctx_reg(get_gpregs_ctx(&optee_ctx->cpu_ctx),
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CTX_GPREG_X0,
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suspend_level);
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max_off_pwrlvl);
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cm_set_elr_el3(SECURE, (uint64_t) &optee_vectors->cpu_resume_entry);
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rc = opteed_synchronous_sp_entry(optee_ctx);
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@ -82,7 +82,7 @@ static int32_t tspd_cpu_off_handler(uint64_t unused)
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* This cpu is being suspended. S-EL1 state must have been saved in the
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* resident cpu (mpidr format) if it is a UP/UP migratable TSP.
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******************************************************************************/
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static void tspd_cpu_suspend_handler(uint64_t unused)
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static void tspd_cpu_suspend_handler(uint64_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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@ -157,7 +157,7 @@ static void tspd_cpu_on_finish_handler(uint64_t unused)
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* completed the preceding suspend call. Use that context to program an entry
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* into the TSP to allow it to do any remaining book keeping
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******************************************************************************/
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static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
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static void tspd_cpu_suspend_finish_handler(uint64_t max_off_pwrlvl)
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{
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int32_t rc = 0;
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uint32_t linear_id = plat_my_core_pos();
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@ -166,10 +166,10 @@ static void tspd_cpu_suspend_finish_handler(uint64_t suspend_level)
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assert(tsp_vectors);
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assert(get_tsp_pstate(tsp_ctx->state) == TSP_PSTATE_SUSPEND);
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/* Program the entry point, suspend_level and enter the SP */
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/* Program the entry point, max_off_pwrlvl and enter the SP */
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write_ctx_reg(get_gpregs_ctx(&tsp_ctx->cpu_ctx),
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CTX_GPREG_X0,
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suspend_level);
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max_off_pwrlvl);
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cm_set_elr_el3(SECURE, (uint64_t) &tsp_vectors->cpu_resume_entry);
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rc = tspd_synchronous_sp_entry(tsp_ctx);
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@ -76,6 +76,8 @@ static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl,
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entry_point_info_t *ep,
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psci_power_state_t *state_info)
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{
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unsigned int max_off_lvl = psci_find_max_off_lvl(state_info);
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/* Save PSCI target power level for the suspend finisher handler */
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psci_set_suspend_pwrlvl(end_pwrlvl);
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@ -91,7 +93,7 @@ static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl,
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_suspend)
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psci_spd_pm->svc_suspend(0);
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psci_spd_pm->svc_suspend(max_off_lvl);
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/*
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* Store the re-entry information for the non-secure world.
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@ -105,7 +107,7 @@ static void psci_suspend_to_pwrdown_start(unsigned int end_pwrlvl,
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* TODO : Introduce a mechanism to query the cache level to flush
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* and the cpu-ops power down to perform from the platform.
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*/
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psci_do_pwrdown_cache_maintenance(psci_find_max_off_lvl(state_info));
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psci_do_pwrdown_cache_maintenance(max_off_lvl);
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}
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/*******************************************************************************
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@ -213,7 +215,7 @@ void psci_cpu_suspend_finish(unsigned int cpu_idx,
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psci_power_state_t *state_info)
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{
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unsigned long long counter_freq;
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unsigned int suspend_level;
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unsigned int max_off_lvl;
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/* Ensure we have been woken up from a suspended state */
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assert(psci_get_aff_info_state() == AFF_STATE_ON && is_local_state_off(\
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@ -245,9 +247,9 @@ void psci_cpu_suspend_finish(unsigned int cpu_idx,
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* error, it's expected to assert within
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*/
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if (psci_spd_pm && psci_spd_pm->svc_suspend) {
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suspend_level = psci_get_suspend_pwrlvl();
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assert (suspend_level != PSCI_INVALID_PWR_LVL);
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psci_spd_pm->svc_suspend_finish(suspend_level);
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max_off_lvl = psci_find_max_off_lvl(state_info);
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assert (max_off_lvl != PSCI_INVALID_PWR_LVL);
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psci_spd_pm->svc_suspend_finish(max_off_lvl);
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}
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/* Invalidate the suspend level for the cpu */
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