From ab74206b605eb6e8d573de15161bb14971556714 Mon Sep 17 00:00:00 2001 From: Samuel Holland Date: Sun, 13 Dec 2020 20:45:49 -0600 Subject: [PATCH] refactor(plat/allwinner): map SRAM as device memory by default The SRAM on Allwinner platforms is shared between BL31 and coprocessor firmware. Previously, SRAM was mapped as normal memory by default. This scheme requires carveouts and cache maintenance code for proper synchronization with the coprocessor. A better scheme is to only map pages owned by BL31 as normal memory, and leave everything else as device memory. This removes the need for cache maintenance, and it makes the mapping for BL31 RW data explicit instead of magic. Signed-off-by: Samuel Holland Change-Id: I820ddeba2dfa2396361c2322308c0db51b55c348 --- plat/allwinner/common/include/platform_def.h | 4 ++-- plat/allwinner/common/sunxi_common.c | 16 ++++++++++++---- plat/allwinner/common/sunxi_scpi_pm.c | 1 - plat/allwinner/sun50i_a64/sunxi_power.c | 1 - 4 files changed, 14 insertions(+), 8 deletions(-) diff --git a/plat/allwinner/common/include/platform_def.h b/plat/allwinner/common/include/platform_def.h index fa0c0abfa..e6ca6010f 100644 --- a/plat/allwinner/common/include/platform_def.h +++ b/plat/allwinner/common/include/platform_def.h @@ -52,8 +52,8 @@ #define CACHE_WRITEBACK_SHIFT 6 #define CACHE_WRITEBACK_GRANULE (1 << CACHE_WRITEBACK_SHIFT) -#define MAX_STATIC_MMAP_REGIONS 5 -#define MAX_MMAP_REGIONS (3 + MAX_STATIC_MMAP_REGIONS) +#define MAX_STATIC_MMAP_REGIONS 4 +#define MAX_MMAP_REGIONS (5 + MAX_STATIC_MMAP_REGIONS) #define PLAT_CSS_SCP_COM_SHARED_MEM_BASE \ (SUNXI_SRAM_A2_BASE + SUNXI_SRAM_A2_SIZE - 0x200) diff --git a/plat/allwinner/common/sunxi_common.c b/plat/allwinner/common/sunxi_common.c index 9d1b3c1ea..d60d767ae 100644 --- a/plat/allwinner/common/sunxi_common.c +++ b/plat/allwinner/common/sunxi_common.c @@ -16,11 +16,7 @@ static const mmap_region_t sunxi_mmap[MAX_STATIC_MMAP_REGIONS + 1] = { MAP_REGION_FLAT(SUNXI_SRAM_BASE, SUNXI_SRAM_SIZE, - MT_RW_DATA | MT_SECURE), -#ifdef SUNXI_SCP_BASE - MAP_REGION_FLAT(SUNXI_SCP_BASE, SUNXI_SCP_SIZE, MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), -#endif MAP_REGION_FLAT(SUNXI_DEV_BASE, SUNXI_DEV_SIZE, MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER), MAP_REGION(SUNXI_DRAM_BASE, SUNXI_DRAM_VIRT_BASE, SUNXI_DRAM_SEC_SIZE, @@ -40,12 +36,24 @@ void sunxi_configure_mmu_el3(int flags) mmap_add_region(BL_CODE_BASE, BL_CODE_BASE, BL_CODE_END - BL_CODE_BASE, MT_CODE | MT_SECURE); + mmap_add_region(BL_CODE_END, BL_CODE_END, + BL_END - BL_CODE_END, + MT_RW_DATA | MT_SECURE); +#if SEPARATE_CODE_AND_RODATA mmap_add_region(BL_RO_DATA_BASE, BL_RO_DATA_BASE, BL_RO_DATA_END - BL_RO_DATA_BASE, MT_RO_DATA | MT_SECURE); +#endif +#if SEPARATE_NOBITS_REGION + mmap_add_region(BL_NOBITS_BASE, BL_NOBITS_BASE, + BL_NOBITS_END - BL_NOBITS_BASE, + MT_RW_DATA | MT_SECURE); +#endif +#if USE_COHERENT_MEM mmap_add_region(BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_BASE, BL_COHERENT_RAM_END - BL_COHERENT_RAM_BASE, MT_DEVICE | MT_RW | MT_SECURE | MT_EXECUTE_NEVER); +#endif mmap_add(sunxi_mmap); init_xlat_tables(); diff --git a/plat/allwinner/common/sunxi_scpi_pm.c b/plat/allwinner/common/sunxi_scpi_pm.c index 74763ef7e..eb37daa63 100644 --- a/plat/allwinner/common/sunxi_scpi_pm.c +++ b/plat/allwinner/common/sunxi_scpi_pm.c @@ -212,7 +212,6 @@ int sunxi_set_scpi_psci_ops(const plat_psci_ops_t **psci_ops) uint32_t offset = SUNXI_SCP_BASE - vector; mmio_write_32(vector, offset >> 2); - clean_dcache_range(vector, sizeof(uint32_t)); } /* Take the SCP out of reset. */ diff --git a/plat/allwinner/sun50i_a64/sunxi_power.c b/plat/allwinner/sun50i_a64/sunxi_power.c index 0fdb62d05..a35b9ddc0 100644 --- a/plat/allwinner/sun50i_a64/sunxi_power.c +++ b/plat/allwinner/sun50i_a64/sunxi_power.c @@ -244,7 +244,6 @@ void sunxi_cpu_power_off_self(void) * in instruction granularity (32 bits). */ mmio_write_32(arisc_reset_vec, ((uintptr_t)code - arisc_reset_vec) / 4); - clean_dcache_range(arisc_reset_vec, 4); /* De-assert the arisc reset line to let it run. */ mmio_setbits_32(SUNXI_R_CPUCFG_BASE, BIT(0));