Tegra186: enable support for simulation environment
The Tegra simulation environment has limited capabilities. This patch checks the chip's major and minor versions to decide the features to enable/disable - MCE firmware version checking is disabled and limited Memory Controller settings are enabled Change-Id: I258a807cc3b83cdff14a9975b4ab4f9d1a9d7dcf Signed-off-by: Varun Wadekar <vwadekar@nvidia.com>
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@ -495,7 +495,7 @@ void tegra_memctrl_setup(void)
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uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
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uint32_t num_overrides = sizeof(streamid_overrides) / sizeof(uint32_t);
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uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
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uint32_t num_sec_cfgs = sizeof(sec_cfgs) / sizeof(mc_streamid_security_cfg_t);
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uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
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uint32_t num_txn_overrides = sizeof(mc_override_cfgs) / sizeof(mc_txn_override_cfg_t);
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uint32_t tegra_rev;
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uint32_t chip_minor, chip_major;
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int i;
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int i;
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INFO("Tegra Memory Controller (v2)\n");
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INFO("Tegra Memory Controller (v2)\n");
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@ -543,10 +543,12 @@ void tegra_memctrl_setup(void)
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/*
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/*
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* Set the MC_TXN_OVERRIDE registers for write clients.
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* Set the MC_TXN_OVERRIDE registers for write clients.
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*/
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*/
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tegra_rev = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) &
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chip_major = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
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HARDWARE_MINOR_REVISION_MASK) >> HARDWARE_MINOR_REVISION_SHIFT;
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MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
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chip_minor = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
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MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
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if (tegra_rev == HARDWARE_REVISION_A01) {
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if ((chip_major == 0) || (chip_major > 0 && chip_minor == 1)) {
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/* GPU and NVENC settings for rev. A01 */
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/* GPU and NVENC settings for rev. A01 */
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val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
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val = tegra_mc_read_32(MC_TXN_OVERRIDE_CONFIG_GPUSWR);
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@ -78,9 +78,11 @@
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******************************************************************************/
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******************************************************************************/
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#define TEGRA_MISC_BASE 0x00100000
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#define TEGRA_MISC_BASE 0x00100000
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#define HARDWARE_REVISION_OFFSET 0x4
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#define HARDWARE_REVISION_OFFSET 0x4
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#define HARDWARE_MINOR_REVISION_MASK 0xf0000
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#define MAJOR_VERSION_SHIFT 0x4
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#define HARDWARE_MINOR_REVISION_SHIFT 0x10
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#define MAJOR_VERSION_MASK 0xF
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#define HARDWARE_REVISION_A01 1
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#define MINOR_VERSION_SHIFT 0x10
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#define MINOR_VERSION_MASK 0xF
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#define MISCREG_PFCFG 0x200C
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#define MISCREG_PFCFG 0x200C
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/*******************************************************************************
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/*******************************************************************************
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@ -457,7 +457,7 @@ void mce_verify_firmware_version(void)
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arch_mce_ops_t *ops;
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arch_mce_ops_t *ops;
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uint32_t cpu_ari_base;
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uint32_t cpu_ari_base;
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uint64_t version;
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uint64_t version;
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uint32_t major, minor;
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uint32_t major, minor, chip_minor, chip_major;
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/* get a pointer to the CPU's arch_mce_ops_t struct */
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/* get a pointer to the CPU's arch_mce_ops_t struct */
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ops = mce_get_curr_cpu_ops();
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ops = mce_get_curr_cpu_ops();
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@ -476,6 +476,17 @@ void mce_verify_firmware_version(void)
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INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
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INFO("MCE Version - HW=%d:%d, SW=%d:%d\n", major, minor,
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TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
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TEGRA_ARI_VERSION_MAJOR, TEGRA_ARI_VERSION_MINOR);
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/*
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* MCE firmware is not running on simulation platforms. Simulation
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* platforms are identified by v0.3 from the Tegra Chip ID value.
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*/
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chip_major = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
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MAJOR_VERSION_SHIFT) & MAJOR_VERSION_MASK;
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chip_minor = (mmio_read_32(TEGRA_MISC_BASE + HARDWARE_REVISION_OFFSET) >>
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MINOR_VERSION_SHIFT) & MINOR_VERSION_MASK;
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if ((chip_major == 0) && (chip_minor == 3))
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return;
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/*
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/*
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* Verify that the MCE firmware version and the interface header
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* Verify that the MCE firmware version and the interface header
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* match
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* match
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